公开(公告)号：US12135644B2

公开(公告)日：2024-11-05

申请号：US18059958

申请日：2022-11-29

Applicant: NETLIST, INC.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/0802 ,  G11C5/04 ,  G11C7/10 ,  G11C29/02

Abstract: A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in one or more ranks and in a plurality of groups, and circuits configurable to receive from the memory controller a system clock and input control and address (C/A) signals, and output registered C/A signals and buffer control signals. The memory module further comprises a plurality of buffer circuits. In response to the buffer control signals, each buffer circuit is configured to communicate first data/strobe signals with at least one memory device and to communicate second data/strobe signals with the memory controller.
The buffer circuit includes at least one delay circuit configured to delay at least one signal of the first data/strobe signals based on a first delay and a second delay. A respective local clock signal has a respective phase relationship with the module clock signal and is output to a corresponding group of the memory devices that includes at least one corresponding memory device in each of the one or more ranks.

公开(公告)号：US11513955B2

公开(公告)日：2022-11-29

申请号：US17141978

申请日：2021-01-05

Applicant: NETLIST, INC.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/0802 ,  G11C5/04 ,  G11C29/02 ,  G11C7/10

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals and a system clock from the memory controller and to output a module clock, module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in one or more ranks, while the data buffer control signals, together with the module clock, are provided to a plurality of buffer circuits corresponding to respective groups of memory devices and are used to control data paths in the buffer circuits. The plurality of buffer circuits include clock regeneration circuits to regenerate clock signals with programmable delays from the module clock. The regenerated clock signals are provided to respective groups of memory devices so as to locally sync the buffer circuits with respective groups of memory devices.

公开(公告)号：US10268608B2

公开(公告)日：2019-04-23

申请号：US15820076

申请日：2017-11-21

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16 ,  G06F3/06 ,  G11C16/00 ,  G11C5/04 ,  G11C7/10 ,  G06F1/10 ,  G06F13/28 ,  G06F13/40 ,  G11C8/18 ,  G11C29/02 ,  G11C8/12 ,  G11C7/20 ,  G11C29/04

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data/strobe signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit includes a data path corresponding to each data signal line in the corresponding set of data/strobe signal lines, and a command processing circuit configured to decode module control signals from the module control circuit and to control the data path in accordance with the module control signals. The data path corresponding to the each data signal line includes at least one tristate buffer controlled by the command processing circuit and a delay circuit configured to delay a signal through the data path by an amount determined by the command processing circuit in response to at least one of the module control signals.

公开(公告)号：US20180300267A1

公开(公告)日：2018-10-18

申请号：US15857519

申请日：2017-12-28

Applicant: Netlist, Inc.

Inventor： Jeffrey C. Solomon ,  Jayesh R. Bhakta

IPC: G06F13/16 ,  G11C5/04 ,  G11C15/00 ,  G11C7/10 ,  G06F13/00 ,  G06F13/42 ,  G06F12/00

Abstract: A memory module operable to communicate data with a memory controller via a data bus comprises a plurality of memory integrated circuits including first memory integrated circuits and second memory integrated circuits, a data buffer coupled between the first memory integrated circuits and the data bus, and between the second memory integrated circuits and the data bus, and logic coupled to the data buffer. The logic is configured to respond to a first memory command by providing first control signals to the data buffer to enable communication of at least one first data signal between the first memory integrated circuits and the memory controller through the data buffer, and is further configured to respond to a second memory command by providing second control signals to the data buffer to enable communication of at least one second data signal between the second memory integrated circuit and the memory controller through the data buffer.

公开(公告)号：US09846659B1

公开(公告)日：2017-12-19

申请号：US14715491

申请日：2015-05-18

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Jeffrey C. Solomon ,  Mario Jesus Martinez ,  Chi-She Chen

IPC: G06F12/00 ,  G06F13/16 ,  G11C5/02 ,  G11C5/06 ,  G11C8/18 ,  G06F13/40

CPC classification number: G06F13/1684 ,  G06F13/4027 ,  G11C5/02 ,  G11C5/06 ,  G11C8/18 ,  H05K1/0216 ,  H05K1/0243 ,  H05K2201/10053 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

公开(公告)号：US20170337125A1

公开(公告)日：2017-11-23

申请号：US15470856

申请日：2017-03-27

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/00 ,  G11C5/06 ,  G11C5/04 ,  G11C8/12 ,  G11C5/02

CPC classification number: G06F12/00 ,  G11C5/025 ,  G11C5/04 ,  G11C5/066 ,  G11C8/12

Abstract: A memory module is configured to communicate with a memory controller. The memory module comprises DDR DRAM devices arranged in multiple ranks each of the same width as the memory module, and a module controller configured to receive and register input control signals for a read or write operation from the memory controller and to output registered address and control signals. The registered address and control signals selects one of the multiple ranks to perform the read or write operation. The module controller further outputs a set of module control signals in response to the input address and control signals. The memory module further comprises a plurality of byte-wise buffers controlled by the set of module control signals to actively drive respective byte-wise sections of each data signal associated with the read or write operation between the memory controller and the selected rank.

公开(公告)号：US09037809B1

公开(公告)日：2015-05-19

申请号：US14324990

申请日：2014-07-07

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Jeffrey C. Solomon ,  Mario Jesus Martinez ,  Chi-She Chen

IPC: G06F12/00 ,  G11C5/02

CPC classification number: G06F13/1684 ,  G06F13/4027 ,  G11C5/02 ,  G11C5/06 ,  G11C8/18 ,  H05K1/0216 ,  H05K1/0243 ,  H05K2201/10053 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

Abstract translation: 本文描述的某些实施例包括具有印刷电路板的存储器模块，该印刷电路板包括被配置为可操作地耦合到计算机系统的存储器控​​制器的至少一个连接器。 存储器模块还包括印刷电路板上的多个存储器件和包括可操作地耦合到至少一个存储器件的第一组端口的电路。 电路还包括可操作地耦合到至少一个连接器的第二组端口。 电路包括切换电路，其被配置为选择性地将第二组端口的一个或多个端口耦合到第一组端口的一个或多个端口。 第一组和第二组的每个端口包括校正电路，其减少在第一组端口和第二组端口之间传输的一个或多个信号中的噪声。

公开(公告)号：US12222878B2

公开(公告)日：2025-02-11

申请号：US17403832

申请日：2021-08-16

Applicant: Netlist, Inc.

Inventor： Jefferey C. Solomon ,  Jayesh R. Bhakta

IPC: G06F13/16 ,  G06F12/00 ,  G06F13/00 ,  G06F13/42 ,  G11C5/04 ,  G11C7/10 ,  G11C15/00

Abstract: A memory module operable to communicate data with a memory controller via a memory bus. The memory module comprises memory devices and logic configurable to receive and register a set of input address and control signals associated with a read or write memory command and to output data transfer control signals. The memory module further comprises circuitry coupled between the memory bus and the memory devices. The circuitry is configurable to be in any of a plurality of states including a first state and a second state, and to transition from the first state to the second state in response to the data transfer control signals. The circuitry in the first state is configured to disable signal communication through the circuitry. The circuitry in the second state is configured to transfer the data signals associated with the read or write command in accordance with a transfer time budget of the memory module.

公开(公告)号：US20230385192A1

公开(公告)日：2023-11-30

申请号：US18325081

申请日：2023-05-29

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0871 ,  G06F3/06 ,  G11C7/10 ,  G06F13/28 ,  G06F13/10 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F12/08 ,  G06F12/0871 ,  G06F3/061 ,  G11C7/1072 ,  G06F13/28 ,  G06F3/068 ,  G06F3/0685 ,  G06F13/10 ,  G06F12/0638 ,  G06F2212/205 ,  G06F3/0688 ,  G06F12/0897

Abstract: A memory module comprises dynamic random access memory (DRAM), Flash memory, and a module controller. The module controller is configured to receive data to be transferred from the DRAM to the Flash memory, compute first cyclic redundancy check (CRC) codes for the data, and write the data into the Flash memory. The module controller is further configured to read the data from the Flash memory, compute second CRC codes for the data read from the Flash memory, and transfer the data to the DRAM. The module controller is further configured to compare the second CRC codes with the first CRC codes to determine one or more erroneous data bits in the data read from the Flash memory, read a data segment of the data from the DRAM that include the one or more erroneous data bits, correct the one or more erroneous data bits in the data segment, and write the data segment back into the DRAM.

公开(公告)号：US10860506B2

公开(公告)日：2020-12-08

申请号：US16391151

申请日：2019-04-22

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16 ,  G06F3/06 ,  G11C5/04 ,  G11C7/10 ,  G11C29/02 ,  G11C16/00 ,  G06F1/10 ,  G06F13/28 ,  G06F13/40 ,  G11C8/18 ,  G11C8/12 ,  G11C7/20 ,  G11C29/04

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.