公开(公告)号：US11048433B2

公开(公告)日：2021-06-29

申请号：US16542308

申请日：2019-08-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F13/00 ,  G06F13/28

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The memory control method includes: performing a first write operation to write first data to a first physical unit in a first physical group through a first channel; performing a limited data collection operation to collect second data, wherein the limited data collection operation limits that the second data does not include data to be collected from the first physical group after the first write operation is completed; and performing a second write operation during a period of performing the first write operation, so as to write the second data to a second physical unit in the second physical group through a second channel. In addition, the limited data collection operation and the second write operation are configured to release at least one spare physical unit.

公开(公告)号：US10997067B2

公开(公告)日：2021-05-04

申请号：US16209986

申请日：2018-12-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F12/02 ,  G06F3/06 ,  G11C16/34 ,  G11C29/52 ,  G11C11/56

Abstract: A data storing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a first data; determining whether a wear degree value of a rewritable non-volatile memory module is less than a threshold; if the wear degree value of the rewritable non-volatile memory module is less than the threshold, storing the first data into the rewritable non-volatile memory module by using a first mode; and if the wear degree value of the rewritable non-volatile memory module is not less than the threshold, storing the first data into the rewritable non-volatile memory module by using a second mode. A reliability of the first data stored by using the first mode is higher than a reliability of the first data stored by using the second mode.

公开(公告)号：US20200186171A1

公开(公告)日：2020-06-11

申请号：US16788320

申请日：2020-02-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Hsiang Lin ,  Shao-Wei Yen ,  Chih-Kang Yeh

IPC: H03M13/29 ,  G06F11/10

Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: obtaining a data; encoding a plurality of sub-data in the data to obtain a plurality of first error checking and correction codes respectively corresponding to the plurality of sub-data; writing the plurality of sub-data and the plurality of first error checking and correction codes into a first physical programming unit; encoding the plurality of sub-data to obtain a second error checking and correction code; and writing the second error checking and correction code into a second physical programming unit.

公开(公告)号：US10565052B2

公开(公告)日：2020-02-18

申请号：US15908831

申请日：2018-03-01

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C29/04

Abstract: A data protecting method, a memory control circuit unit and a memory storage apparatus are provided. The method includes generating a first temporary parity code group based on first data written into a first super physical unit; generating a second temporary parity code group by performing a logic operation on second data written into a second super physical unit and the first temporary parity code group; and generating an updated parity code group by performing the logic operation on the second temporary parity code group and the first data when data of the first super physical unit all become invalid data.

公开(公告)号：US20190196903A1

公开(公告)日：2019-06-27

申请号：US15908831

申请日：2018-03-01

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: A data protecting method, a memory control circuit unit and a memory storage apparatus are provided. The method includes generating a first temporary parity code group based on first data written into a first super physical unit; generating a second temporary parity code group by performing a logic operation on second data written into a second super physical unit and the first temporary parity code group; and generating an updated parity code group by performing the logic operation on the second temporary parity code group and the first data when data of the first super physical unit all become invalid data.

公开(公告)号：US10283196B2

公开(公告)日：2019-05-07

申请号：US15238715

申请日：2016-08-16

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh ,  Po-Yung Chang

IPC: G06F12/00 ,  G11C11/56 ,  G06F3/06

Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes grouping physical erasing units of a rewritable non-volatile memory module at least into a first area and a second area, wherein the second area is programmed with a single-page programming mode and the first area is programmed with a multi-page programming mode. The method further includes receiving first data; and determining whether the number of a physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is less than a predetermined value, and if yes, writing the first data into the physical erasing units of the second area.

公开(公告)号：US20190114226A1

公开(公告)日：2019-04-18

申请号：US15820461

申请日：2017-11-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Chih-Kang Yeh ,  Yu-Cheng Hsu ,  Szu-Wei Chen

IPC: G06F11/10 ,  G06F3/06 ,  H03M13/29 ,  G11C29/52

Abstract: A data encoding method, a memory control circuit unit and a memory storage device are provided. The method includes: writing a first data into a first physical programming units; writing a second data into a second physical programming units; encoding by using the first data without using the second data to generate a first encoded data; encoding by using the second data and a first sub-data of the first data to generate a second encoded data; and writing the first encoded data and the second encoded data into a third physical programming unit and a fourth physical programming unit.

公开(公告)号：US10191840B2

公开(公告)日：2019-01-29

申请号：US14829654

申请日：2015-08-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh ,  Chang-Han Hsieh

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/02 ,  G06F3/06 ,  G06F12/1009

Abstract: A mapping table updating method for a rewritable non-volatile memory module is provided. The method includes: allocating a mapping table storage area for storing a physical address-logical address mapping table in a buffer memory. The method also includes: determining whether a remaining storage space of the mapping table storage area is less than a threshold. If the remaining storage space is less than the threshold, mapping information of the physical address-logical address mapping table stored in the mapping table storage area is updated into at least one logical address-physical address mapping table, and the mapping information of the physical address-logical address mapping table stored in the mapping table storage area is cleared. The method also includes: storing updated mapping information corresponding to a programmed active physical erasing unit into the mapping table storage area.

公开(公告)号：US10001928B2

公开(公告)日：2018-06-19

申请号：US15390547

申请日：2016-12-26

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0608 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided, wherein the memory storage device includes a rewritable non-volatile memory module and a buffer memory. The method includes: loading at least one first address information of at least one first logical-physical mapping table from the rewritable non-volatile memory module to a first buffer area when the memory storage device is operated in a first mode, wherein the first address information has a first data quantity; and loading at least one second address information of at least one second logical-physical mapping table from the rewritable non-volatile memory module to the first buffer area when the memory storage device is operated in a second mode, wherein the second address information has a second data quantity, and the first data quantity is less than the second data quantity.

公开(公告)号：US20180143778A1

公开(公告)日：2018-05-24

申请号：US15413427

申请日：2017-01-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0617 ,  G06F3/0652 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A data storage method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a first space in a first physical unit of a rewritable non-volatile memory module; and storing at least part of data stored in at least one physical unit of the rewritable non-volatile memory module to a second space in the first physical unit, and the second space is not belonging to the first space, and the first space is for ensuring that valid data stored in at least one second physical unit among the at least one physical unit can be stored to the first physical unit. Therefore, it is ensured that at least one spare physical unit of the memory storage device can be released by a data merging operation of multiple source nodes.