公开(公告)号：US10020028B2

公开(公告)日：2018-07-10

申请号：US15351600

申请日：2016-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G06F17/50 ,  G11C5/04 ,  G11C5/06 ,  H05K1/18 ,  G11C5/02 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H05K1/02 ,  H05K3/46

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

公开(公告)号：US09991221B2

公开(公告)日：2018-06-05

申请号：US15782182

申请日：2017-10-12

Applicant: Renesas Electronics Corporation

Inventor： Jun Yamada ,  Takafumi Betsui

IPC: H05K7/10 ,  H05K7/12 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/48 ,  H01L23/14 ,  H01L23/31 ,  H05K3/32

CPC classification number: H01L24/33 ,  H01L23/145 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/065 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/13009 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/13578 ,  H01L2224/13611 ,  H01L2224/13686 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/335 ,  H01L2224/33515 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15333 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K3/323 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/04941

Abstract: A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc., in which a semiconductor chip is mounted over an interposer, such as a multilayer organic wiring board, in a face-up manner, a first group of metal through electrodes, which are provided in the semiconductor chip to supply a power supply potential to a core circuit, etc., and a first metal land over the interposer are interconnected by a first conductive adhesive member film.

公开(公告)号：US09990981B2

公开(公告)日：2018-06-05

申请号：US15178091

申请日：2016-06-09

Applicant: Renesas Electronics Corporation

Inventor： Motoo Suwa ,  Takafumi Betsui

IPC: G11C11/4076 ,  H01L23/498 ,  H01L27/108 ,  H01L23/538 ,  G11C5/06

CPC classification number: G11C11/4076 ,  G11C5/063 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L27/108 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: To provide an electronic device capable of improving a signal quality, the electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.

公开(公告)号：US09839130B1

公开(公告)日：2017-12-05

申请号：US15480353

申请日：2017-04-05

Applicant: Renesas Electronics Corporation

Inventor： Takafumi Betsui

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/46 ,  H05K3/30 ,  H01L23/495

CPC classification number: H05K1/182 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49589 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/183 ,  H05K1/185 ,  H05K3/301 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4697

Abstract: A semiconductor integrated circuit device (101) includes a component built-in board (21) in which at least a first core layer (Co21) on which a first electronic component (C21) is mounted, a second core layer (Co22) on which a second electronic component (C22) is mounted, an adhesive layer (Ad21) arranged between the first core layer (Co21) and the second core layer (Co22), and wiring layers (L21-L28) are stacked; a third electronic component (SoC) mounted in a first core layer (Co21) side of the component built-in board (21) and electrically connected to at least one of the first and second electronic components (C21, C22) through the wiring layers (L21 to L28); and an external connection terminal (BE) formed in a second core layer (Co22) side of the component built-in board (21) and electrically connected to at least one of the first and second electronic components (C21, C22).

公开(公告)号：US09792959B2

公开(公告)日：2017-10-17

申请号：US15351580

申请日：2016-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G11C5/04 ,  G11C5/06 ,  H05K1/18 ,  G11C5/02 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H05K1/02 ,  H05K3/46

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

公开(公告)号：US09673142B2

公开(公告)日：2017-06-06

申请号：US15207559

申请日：2016-07-12

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki Sakata ,  Takafumi Betsui

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/563 ,  H01L22/32 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/06133 ,  H01L2224/06136 ,  H01L2224/06155 ,  H01L2224/06177 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14133 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/16238 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2224/49175 ,  H01L2224/49179 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A semiconductor device with enhanced reliability. The semiconductor device has a wiring substrate which includes a first terminal electrically connected with a power supply potential supply section of a semiconductor chip, a first wiring coupling the power supply potential supply section with the first terminal, a second terminal electrically connected with a reference potential supply section of the semiconductor chip, and a second wiring coupling the reference potential supply section with the second terminal. The first terminal and second terminal are arranged closer to the periphery of the wiring substrate than the semiconductor chip. The second wiring is extended along the first wiring.

公开(公告)号：US20140097547A1

公开(公告)日：2014-04-10

申请号：US14037620

申请日：2013-09-26

Applicant: Renesas Electronics Corporation

Inventor： Atsushi Kuroda ,  Takafumi Betsui

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/09 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: This invention is to improve noise immunity to the power supply and ground of a wiring board and a second semiconductor chip in an interior of a semiconductor device. A first semiconductor chip is mounted over a wiring board, and a second semiconductor chip is mounted in a central part located over the first semiconductor chip. Bottom surface electrodes of power and ground systems in the second semiconductor chip are led to their corresponding external coupling electrodes formed in the central part of the wiring board though chip through vias formed in the central part of the first semiconductor chip. The power and ground system bottom surface electrodes, the through vias and the external coupling electrodes are respectively arranged discretely from each other between the power and ground systems.

Abstract translation: 本发明是为了提高对半导体器件内部的布线板和第二半导体芯片的电源和接地的抗干扰性。 第一半导体芯片安装在布线板上，第二半导体芯片安装在位于第一半导体芯片上方的中心部分。 第二半导体芯片中的电源和接地系统的底表面电极通过形成在第一半导体芯片的中心部分中的通孔的芯片通过形成在布线板的中心部分的对应的外部耦合电极被引导。 电力和地面系统底面电极，通孔和外部耦合电极分别在电源和地面系统之间彼此离散布置。