公开(公告)号：US20240237216A9

公开(公告)日：2024-07-11

申请号：US18491456

申请日：2023-10-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Oseob JEON ,  Seungwon IM ,  Rajani Kumar THIRUKOLURI ,  Roveendra PAUL

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/18 ,  H05K1/11 ,  H05K2201/10166

Abstract: In a general aspect, a half-bridge circuit includes a substrate having first, second and third patterned metal layers disposed on a surface. The circuit also includes first and second high-side transistors disposed on the first patterned metal layer, and first and conductive clips electrically coupling, respectively, the first and second high-side transistors with the second patterned metal layer. The circuit also includes first and second low-side transistors disposed on the second patterned metal layer, and third and fourth conductive clips electrically coupling, respectively, the first and second low-side transistors with the third patterned metal layer. The circuit further includes a DC+ terminal electrically coupled with the first patterned metal layer via a first conductive post disposed between the first and second high-side transistors, and a DC− terminal electrically coupled with the third patterned metal layer via a second conductive post disposed between the third and fourth conductive clips.

公开(公告)号：US20240088007A1

公开(公告)日：2024-03-14

申请号：US17931665

申请日：2022-09-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jonghwan BAEK ,  Jeonghyuk PARK ,  Seungwon IM ,  Keunhyuk LEE ,  Dukyong LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16

CPC classification number: H01L23/49833 ,  H01L21/4825 ,  H01L21/4839 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49844 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48139 ,  H01L2224/48145 ,  H01L2224/48175 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2924/12036 ,  H01L2924/13055

Abstract: A package includes a first direct bonded metal (DBM) substrate, a first semiconductor die disposed on a top surface of the first DBM substrate, a second DBM substrate disposed at a height above the first DBM substrate, and a second semiconductor die disposed on a top surface of the second DBM substrate. A wire bond is made between the first semiconductor die disposed on the top surface of the first DBM substrate and the second semiconductor die disposed on the top surface of the second DBM substrate.

公开(公告)号：US20240055334A1

公开(公告)日：2024-02-15

申请号：US18354863

申请日：2023-07-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Oseob JEON ,  Jihwan KIM ,  Dongwook KANG

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L23/3121 ,  H01L21/4853 ,  H01L21/56

Abstract: In a general aspect, an electronic device assembly includes a circuit including at least one semiconductor die, and a signal lead electrically coupled with the circuit. The signal lead has a hole defined therethrough. The assembly further includes an electrically conductive signal pin holder disposed in the hole of the signal lead. The electrically conductive signal pin holder is electrically coupled with the signal lead. The assembly also includes a molding compound encapsulating, at least, the circuit; a portion of the signal lead including the hole; and a portion of the electrically conductive signal pin holder. An open end of the electrically conductive signal pin holder is accessible outside the molding compound.

公开(公告)号：US20220406744A1

公开(公告)日：2022-12-22

申请号：US17664749

申请日：2022-05-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jooyang EOM ,  Seungwon IM ,  Maria Cristina ESTACIO ,  Jerome TEYSSEYRE ,  Inpil YOO

IPC: H01L23/00 ,  H01L23/373

Abstract: Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.

公开(公告)号：US20220208654A1

公开(公告)日：2022-06-30

申请号：US17136340

申请日：2020-12-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jonghwan BAEK ,  JeongHyuk PARK ,  Seungwon IM ,  Keunhyuk LEE

IPC: H01L23/495 ,  H01L23/00

Abstract: Implementations of semiconductor packages may include a substrate, a first die coupled on the substrate, and a lead frame coupled over the substrate. The lead frame may include a die attach pad. Implementations of semiconductor packages may also include a second die coupled on the die attach pad. The second die may overlap the first die.

公开(公告)号：US20210265318A1

公开(公告)日：2021-08-26

申请号：US17316367

申请日：2021-05-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Oseob JEON ,  JoonSeo SON ,  Mankyo JONG ,  Olaf ZSCHIESCHANG

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/07 ,  H01L21/56 ,  H01L23/373 ,  H01L23/00

Abstract: Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal layer; a second substrate having a second dielectric layer coupled between a third metal layer and a fourth metal layer. A first die may be coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate and a second die may be coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate.

公开(公告)号：US20210143107A1

公开(公告)日：2021-05-13

申请号：US16680795

申请日：2019-11-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Oseob JEON

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/48

Abstract: In general aspect, a semiconductor device package can include a substrate and a semiconductor die disposed on and coupled with the substrate. The semiconductor device package can further include a leadframe having an indentation defined therein, at least a portion of the indentation being disposed on and coupled with the semiconductor die via a conductive adhesive.

公开(公告)号：US20200185305A1

公开(公告)日：2020-06-11

申请号：US16790933

申请日：2020-02-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Oseob JEON ,  Byoungok LEE ,  Yoonsoo LEE ,  Joonseo SON ,  Dukyong LEE ,  Changyoung PARK

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/498 ,  H01L23/13 ,  H01L23/495 ,  H01L23/473

Abstract: Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.

公开(公告)号：US20190287886A1

公开(公告)日：2019-09-19

申请号：US16429366

申请日：2019-06-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Maria Cristina ESTACIO ,  Seungwon IM

IPC: H01L23/495 ,  H01L23/433 ,  H01L23/473 ,  H01L23/00 ,  H01L29/16 ,  H01L21/56 ,  H01L23/373 ,  H01L23/31

Abstract: In a general aspect, a method can include forming a first conductive metal layer including a common gate conductor, and coupling a plurality of semiconductor die to the common gate conductor of the first conductive metal layer where the plurality of semiconductor die include a first silicon carbide die and a second silicon carbide die. The method can include encapsulating at least a portion of the first conductive metal layer and the semiconductor die within an insulator where the first conductive metal layer includes a first conductive path between the common gate conductor and a die gate conductor of the first silicon carbide die, and a second conductive path between the common gate conductor and a die gate conductor of the second silicon carbide die. The first conductive path can have a length substantially equal to a length of the second conductive path.

公开(公告)号：US20250140659A1

公开(公告)日：2025-05-01

申请号：US18941178

申请日：2024-11-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Maria Cristina ESTACIO ,  Seungwon IM

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/433 ,  H01L23/473 ,  H10D62/832

Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.