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公开(公告)号:US20240234246A1
公开(公告)日:2024-07-11
申请号:US18616351
申请日:2024-03-26
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Seungwon IM , Oseob JEON , Byoungok LEE , Yoonsoo LEE , Joonseo SON , Dukyong LEE , Changyoung PARK
IPC: H01L23/433 , H01L23/13 , H01L23/24 , H01L23/473 , H01L23/495 , H01L23/498 , H01L25/065
CPC classification number: H01L23/433 , H01L23/13 , H01L23/4334 , H01L23/473 , H01L23/49568 , H01L23/49861 , H01L25/0657 , H01L23/24 , H01L2224/33
Abstract: Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.
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公开(公告)号:US20220093487A1
公开(公告)日:2022-03-24
申请号:US17457100
申请日:2021-12-01
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Seungwon IM , Oseob JEON , Byoungok LEE , Yoonsoo LEE , Joonseo SON , Dukyong LEE , Changyoung PARK
IPC: H01L23/433 , H01L23/13 , H01L23/473 , H01L23/498 , H01L25/065 , H01L23/495
Abstract: Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.
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公开(公告)号:US20200185305A1
公开(公告)日:2020-06-11
申请号:US16790933
申请日:2020-02-14
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Seungwon IM , Oseob JEON , Byoungok LEE , Yoonsoo LEE , Joonseo SON , Dukyong LEE , Changyoung PARK
IPC: H01L23/433 , H01L25/065 , H01L23/498 , H01L23/13 , H01L23/495 , H01L23/473
Abstract: Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.
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公开(公告)号:US20180315681A1
公开(公告)日:2018-11-01
申请号:US15714539
申请日:2017-09-25
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Seungwon IM , Oseob JEON , Byoungok LEE , Yoonsoo LEE , Joonseo SON , Dukyong LEE , Changyoung PARK
IPC: H01L23/433 , H01L23/24 , H01L25/065 , H01L23/498 , H01L23/13
Abstract: Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.
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公开(公告)号:US20240266252A1
公开(公告)日:2024-08-08
申请号:US18165504
申请日:2023-02-07
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Oseob JEON , Yoonsoo LEE , Bosung WON , Youngsun KO
IPC: H01L23/473 , H01L23/367 , H01L23/49 , H05K7/20
CPC classification number: H01L23/473 , H01L23/3672 , H01L23/49 , H05K7/20509
Abstract: Implementations of a dual sided cooling module may include a high side module coupled over a low side module through a coupling heat sink at a first largest planar surface of the high side module and at a first largest planar surface of the low side module; a high side heat sink coupled at a second largest planar surface of the high side module; and a low side heat sink coupled at a second largest planar surface of the low side module. A single cooling fluid may contact the coupling heat sink, the high side heat sink, and the low side heat sink.
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公开(公告)号:US20240162117A1
公开(公告)日:2024-05-16
申请号:US18055123
申请日:2022-11-14
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Yoonsoo LEE , Seungwon IM , Oseob JEON
IPC: H01L23/473 , H01L25/00 , H01L25/07 , H01L25/18
CPC classification number: H01L23/473 , H01L25/071 , H01L25/18 , H01L25/50
Abstract: A package includes a frame having a cooling fluid channel therethrough. The frame has at least one opening in a first sidewall alongside the cooling fluid channel and at least one opening in a second sidewall alongside the cooling fluid channel. A first power electronics module covers the at least one opening in the first sidewall with a surface of a substrate in the first power electronics module being exposed to the cooling fluid channel in the frame through the at least one opening in the first sidewall, and a second power electronics module covers the at least one opening in the second sidewall with a surface of a substrate in the second electronics module being exposed to the cooling fluid channel in the frame through the at least one opening in the second sidewall.
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