公开(公告)号：US20130194764A1

公开(公告)日：2013-08-01

申请号：US13562683

申请日：2012-07-31

Applicant: Yukinobu MIKADO ,  Shunsuke SAKAI ,  Takashi KARIYA ,  Toshiki FURUTANI

Inventor： Yukinobu MIKADO ,  Shunsuke SAKAI ,  Takashi KARIYA ,  Toshiki FURUTANI

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H05K1/185 ,  H01G2/06 ,  H05K1/0207 ,  H05K1/115 ,  H05K3/30 ,  H05K3/32 ,  H05K3/4602 ,  H05K2201/09827 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2203/1469 ,  Y02P70/611 ,  Y10T29/49146

Abstract: A wiring board includes a substrate having an opening portion, electronic components positioned in the opening portion of the substrate and including first and second electronic components, and an insulation layer formed over the substrate and the first and second components. The first component has first and second electrodes having side portions on side surfaces of the first component, the second component has first and second electrodes having side portions on side surfaces of the second component, the first electrode of the first component and the first electrode of the second component are set to have substantially the same electric potential, and the first component and the second component are positioned in the opening portion of the substrate such that the side portion of the first electrode of the first component is beside the side portion of the first electrode of the second component.

公开(公告)号：US20110102122A1

公开(公告)日：2011-05-05

申请号：US12985475

申请日：2011-01-06

Applicant: Yasuhiko MANO ,  Takashi KARIYA ,  Shinobu KATO

Inventor： Yasuhiko MANO ,  Takashi KARIYA ,  Shinobu KATO

IPC: H01F5/00 ,  H05K3/00

CPC classification number: H05K3/4046 ,  H01F17/0006 ,  H01F17/06 ,  H01F41/046 ,  H01F2017/002 ,  H01F2017/065 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0233 ,  H05K1/115 ,  H05K1/185 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/086 ,  H05K2201/09581 ,  Y10T29/4902 ,  H01L2224/05599

Abstract: A printed wiring board including a substrate having a first surface and a second surface on the opposite side of the second surface, a first conductive circuit formed on the first surface of the substrate, a second conductive circuit formed on the second surface of the substrate, a magnetic body embedded in the substrate and extending in a thickness direction of the substrate, the magnetic body having a through-hole formed through the magnetic body and extending in the thickness direction of the substrate, and a through-hole conductor formed on an inner surface of the through-hole of the magnetic body such that the first and second conductive circuits are electrically connected to each other through the through-hole conductor.

Abstract translation: 一种印刷电路板，包括具有在所述第二表面的相对侧上的第一表面和第二表面的基板，形成在所述基板的第一表面上的第一导电电路，形成在所述基板的第二表面上的第二导电电路， 磁性体，其嵌入到所述基板中并沿着所述基板的厚度方向延伸，所述磁性体具有通过所述磁性体形成并在所述基板的厚度方向上延伸的通孔，以及形成在所述基板的内部的通孔导体 磁体的通孔的表面，使得第一和第二导电电路通过通孔导体彼此电连接。

公开(公告)号：US20110100700A1

公开(公告)日：2011-05-05

申请号：US12984644

申请日：2011-01-05

Applicant: Takashi KARIYA ,  Toshiki FURUTANI

Inventor： Takashi KARIYA ,  Toshiki FURUTANI

IPC: H05K1/11

CPC classification number: H05K1/0271 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49151 ,  Y10T29/49162 ,  H01L2224/0401

Abstract: A multilayer printed wiring board 10 includes: a build-up layer 30 that is formed on a core substrate 20 and has a conductor pattern 32 disposed on an upper surface; a low elastic modulus layer 40 that is formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a IC chip 70; and conductor posts 50 that pass through the low elastic modulus layer 40 and electrically connect lands 52 with conductor patterns 32. The conductor posts 50 have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 μm, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer 40, is greater than or equal to the aspect ratio Rasp of internal conductor posts 50b, which are positioned at internal portions of the low elastic modulus layer 40.

Abstract translation: 多层印刷布线板10包括：形成在芯基板20上并具有布置在上表面上的导体图案32的堆积层30; 形成在积层30上的低弹性模量层40; 焊盘52设置在低弹性模量层40的上表面上并通过焊料凸块66连接到IC芯片70; 以及穿过低弹性模量层40并将焊盘52与导体图案32电连接的导体柱50.导体柱50的纵横比Rasp（高度/最小直径）不小于4，最小直径超过30μm ，并且位于低弹性模量层40的外部的外部导体柱50a的纵横比Rasp大于或等于位于内部导体柱50b的内部导体柱50b的纵横比Rasp 低弹性模量层40。

公开(公告)号：US20100108637A1

公开(公告)日：2010-05-06

申请号：US12652255

申请日：2010-01-05

Applicant: Takashi KARIYA ,  Toshiki Furutani

Inventor： Takashi KARIYA ,  Toshiki Furutani

IPC: H01B13/00

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/0271 ,  H05K1/0373 ,  H05K1/111 ,  H05K1/115 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/09881 ,  H05K2201/10674 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49204 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A multilayer printed wiring board manufacturing method including forming conductor posts, which are of substantially uniform thickness and with which the top surfaces are protected by a resist, on a conductor pattern disposed on an upper surface of a build-up layer formed on a core substrate, shaping the conductor posts to have a constriction by adjusting the time of immersion in an etching solution that etches the conductor posts, forming a low elastic modulus layer of substantially the same height as the conductor posts after removing the resist at the top surfaces, and forming mounting electrodes on upper surfaces of the conductor posts.

Abstract translation: 一种多层印刷线路板制造方法，包括形成基本上均匀的厚度并且顶表面被抗蚀剂保护的导体柱布置在形成在芯基板上的积聚层的上表面上的导体图案上 通过调节蚀刻导体柱的蚀刻溶液中的浸渍时间来形成导体柱以形成收缩，在去除顶表面上的抗蚀剂之后形成与导体柱基本上相同的高度的低弹性模量层，以及 在导体柱的上表面上形成安装电极。

公开(公告)号：US20100018049A1

公开(公告)日：2010-01-28

申请号：US12571973

申请日：2009-10-01

Applicant: Hajime SAKAMOTO ,  Tadashi SUGIYAMA ,  Dongdong WANG ,  Takashi KARIYA

Inventor： Hajime SAKAMOTO ,  Tadashi SUGIYAMA ,  Dongdong WANG ,  Takashi KARIYA

IPC: H05K3/30

CPC classification number: H01L24/29 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/83 ,  H01L25/03 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/18162 ,  H01L2924/30107 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09918 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A method of manufacturing a multilayer printed circuit board having interlayer insulating layers and conductor layers repeatedly formed on a substrate, via holes formed in the interlayer insulating layers, and establishing electrical connection through the via holes, including containing an electronic component in said substrate, forming a positioning mark on said substrate based on a positioning mark of said electronic component, and conducting working or formation based on the positioning mark of said substrate.

Abstract translation: 一种制造多层印刷电路板的方法，所述多层印刷电路板具有层间绝缘层和导体层，所述多层印刷电路板重复地形成在基板上，通过形成在所述层间绝缘层中的孔，并且通过所述通孔建立与所述基板中包含电子部件的电连接， 基于所述电子部件的定位标记在所述基板上的定位标记，并且基于所述基板的定位标记进行加工或形成。

公开(公告)号：US20070295532A1

公开(公告)日：2007-12-27

申请号：US11778989

申请日：2007-07-17

Applicant: Takashi KARIYA ,  Toshiki Furutani

Inventor： Takashi KARIYA ,  Toshiki Furutani

IPC: H05K3/46 ,  H05K1/03

CPC classification number: H05K1/0271 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49151 ,  Y10T29/49162 ,  H01L2224/0401

Abstract: A multilayer printed wiring board 10 includes: a build-up layer 30 that is formed on a core substrate 20 and has a conductor pattern 32 disposed on an upper surface; a low elastic modulus layer 40 that is formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a IC chip 70; and conductor posts 50 that pass through the low elastic modulus layer 40 and electrically connect lands 52 with conductor patterns 32. The conductor posts 50 have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 μm, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer 40, is greater than or equal to the aspect ratio Rasp of internal conductor posts 50b, which are positioned at internal portions of the low elastic modulus layer 40.

Abstract translation: 多层印刷布线板10包括：形成在芯基板20上并具有布置在上表面上的导体图案32的堆积层30; 形成在积层30上的低弹性模量层40; 焊盘52设置在低弹性模量层40的上表面上并通过焊锡凸块66连接到IC芯片70; 以及穿过低弹性模量层40并将焊盘52与导体图案32电连接的导体柱50.导体柱50的纵横比Rasp（高度/最小直径）不小于4，最小直径超过30μm ，并且位于低弹性模量层40的外部的外部导体柱50a的纵横比Rasp大于或等于位于内部部分的内部导体柱50b的纵横比Rasp 的低弹性模量层40。