公开(公告)号：US09349822B2

公开(公告)日：2016-05-24

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L27/092

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US20160093536A1

公开(公告)日：2016-03-31

申请号：US14520342

申请日：2014-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/423 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract translation: 本发明提供一种集成电路，其包括衬底，第一晶体管，第二晶体管和第三晶体管。 第一晶体管具有包括第一底部阻挡层，第一功函数金属层和第一金属层的第一金属栅极。 第二晶体管具有包括第二底部阻挡层，第二功函数金属层和第二金属层的第二金属栅极。 第三晶体管具有包括第三底部阻挡层，第三功函数金属层和第三金属层的第三金属栅极。 第一晶体管，第二晶体管和第三晶体管具有相同的导电类型。 第一底部阻挡层的氮浓度>第二底部阻挡层的氮浓度>第三底部阻挡层的氮浓度。

公开(公告)号：US20150357430A1

公开(公告)日：2015-12-10

申请号：US14324092

申请日：2014-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Lung-En Kuo ,  You-Di Jhang ,  Jian-Cun Ke

IPC: H01L29/51 ,  H01L29/40

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在衬底上形成界面层; 在界面层上形成堆叠结构; 图案化堆叠结构以在界面层上形成栅极结构; 在界面层和栅极结构上形成衬垫; 以及去除衬套的一部分和用于形成间隔物的界面层的一部分。

公开(公告)号：US20250098252A1

公开(公告)日：2025-03-20

申请号：US18379667

申请日：2023-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ke-Ting Chen ,  Ching-Ling Lin ,  Wen-An Liang ,  Chia-Fu Hsu

IPC: H01L29/40 ,  H01L21/311 ,  H01L29/417 ,  H01L29/423

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a contact etch stop layer (CESL) adjacent to the metal gate, and an interlayer dielectric (ILD) layer around the gate structure, performing a first etching process to remove the ILD layer, performing a second etching process to remove the CESL for forming a first contact hole, and then forming a first contact plug in the first contact hole. Preferably, a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug under the CESL.

公开(公告)号：US20240371699A1

公开(公告)日：2024-11-07

申请号：US18208896

申请日：2023-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Wen-An Liang ,  Chia-Fu Hsu ,  Huang-Ren Wei

IPC: H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66

Abstract: The invention provides a semiconductor structure, the semiconductor structure comprises a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, a plurality of first metal layers located on a part of the gate structures, and the first metal layers are respectively electrically connected with the corresponding gate structures, at least one second metal layer, the second metal layer is bridged over at least two of the gate structures, wherein the depth of the first metal layer is greater than that of the second metal layer.

公开(公告)号：US10164052B2

公开(公告)日：2018-12-25

申请号：US15667629

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Lung-En Kuo ,  You-Di Jhang ,  Jian-Cun Ke

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.

公开(公告)号：US09972644B2

公开(公告)日：2018-05-15

申请号：US14872156

申请日：2015-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L29/12 ,  H01L27/12 ,  H01L29/786 ,  H01L29/51 ,  H01L29/24 ,  H01L23/528 ,  H01L29/66 ,  H01L21/02 ,  H01L21/441 ,  H01L21/768

CPC classification number: H01L27/1237 ,  H01L21/02107 ,  H01L21/02323 ,  H01L21/02565 ,  H01L21/441 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/512 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device including a substrate, an oxide semiconductor layer, two source/drain regions, a high-k dielectric layer and a bottom oxide layer. The oxide semiconductor layer is disposed on a first insulating layer disposed on the substrate. The source/drain regions are disposed on the oxide semiconductor layer. The high-k dielectric layer covers the oxide semiconductor layer and the source structure and the drain regions. The bottom oxide layer is disposed between the high-k dielectric layer and the source/drain regions, wherein the bottom oxide layer covers the source/drain regions and the oxide semiconductor layer.

公开(公告)号：US20170330954A1

公开(公告)日：2017-11-16

申请号：US15667629

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Lung-En Kuo ,  You-Di Jhang ,  Jian-Cun Ke

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

Abstract: A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.

公开(公告)号：US09761690B2

公开(公告)日：2017-09-12

申请号：US14324092

申请日：2014-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Mao Chiou ,  Shih-Chieh Hsu ,  Lung-En Kuo ,  You-Di Jhang ,  Jian-Cun Ke

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.

公开(公告)号：US20160300755A1

公开(公告)日：2016-10-13

申请号：US14711777

申请日：2015-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tian Choy Gan ,  Chu-Yun Hsiao ,  Chun-Che Huang ,  Chia-Fu Hsu

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/423 ,  H01L21/768

CPC classification number: H01L29/4236 ,  H01L21/02274 ,  H01L21/76224 ,  H01L21/7684 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42384

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

Abstract translation: 半导体工艺包括以下步骤。 在电介质层的沟槽中依次形成金属栅极条和盖层。 切割盖层和金属栅极条以在多个金属栅极上形成多个盖，并且间隙隔离相邻的盖和相邻的金属栅。 隔离材料填补了间隙。 本发明还提供了由所述半导体工艺形成的半导体结构。 例如，半导体结构在电介质层的沟槽中包括多个堆叠结构，其中每个堆叠结构在金属栅极上包括金属栅极和盖子，其中隔离槽在端部隔离并接触相邻堆叠结构 结束，并且隔离槽具有与堆叠结构相同的水平。