公开(公告)号：US09564371B2

公开(公告)日：2017-02-07

申请号：US14514374

申请日：2014-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Tsung-Hung Chang ,  Jia-Rong Wu ,  Ching-Ling Lin ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/823475 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823431

Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.

Abstract translation: 一种半导体器件的制造方法，其特征在于，首先，在基板上形成有基板，在所述散热片结构上形成有多个栅极结构，然后将硬掩模层和第一光致抗蚀剂层 形成在鳍结构上，然后在第一光致抗蚀剂层上进行第一蚀刻工艺，然后在剩余的第一光致抗蚀剂层和剩余的硬掩模层上形成多个图案化的光致抗蚀剂层，其中每个图案化的光致抗蚀剂层被设置 每个栅极结构的正上方，并且每个图案化的光致抗蚀剂的宽度大于每个栅极结构的宽度，并且图案化的光致抗蚀剂层用作硬掩模以执行第二蚀刻工艺以形成多个第二沟槽。

公开(公告)号：US09281374B2

公开(公告)日：2016-03-08

申请号：US14490679

申请日：2014-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsun-Min Cheng ,  Min-Chuan Tsai ,  Chih-Chien Liu ,  Jen-Chieh Lin ,  Pei-Ying Li ,  Shao-Wei Wang ,  Mon-Sen Lin ,  Ching-Ling Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/43 ,  H01L29/772 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4232 ,  H01L29/435 ,  H01L29/51 ,  H01L29/66045 ,  H01L29/66545 ,  H01L29/78

Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Abstract translation: 位于基板上的金属栅极结构包括栅介质层，金属层和氮化铝钛金属层。 栅介质层位于衬底上。 金属层位于栅极电介质层上。 氮化铝钛金属层位于金属层上。

公开(公告)号：US20160064327A1

公开(公告)日：2016-03-03

申请号：US14494607

申请日：2014-09-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Yi-Wei Chen

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0629

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：衬底; 基板上的第一金属栅极; 第一个金属门上的第一个硬掩模; 在第一金属栅极的顶部和周围的层间绝缘层（ILD）层; 以及嵌入ILD层中的图案化金属层，其中图案化金属层的顶表面比第一硬掩模的顶表面低。

公开(公告)号：US09196500B2

公开(公告)日：2015-11-24

申请号：US13859720

申请日：2013-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Chien-Ting Lin

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/3086 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/66795

Abstract: A method for manufacturing semiconductor structures includes providing a substrate having a plurality of mandrel patterns and a plurality of dummy patterns, simultaneously forming a plurality of first spacers on sidewalls of the mandrel patterns and a plurality of second spacers on sidewalls of the dummy patterns, and removing the second spacers and the mandrel patterns to form a plurality of spacer patterns on the substrate.

Abstract translation: 一种用于制造半导体结构的方法，包括提供具有多个心轴图案和多个虚拟图案的基板，同时在心轴图案的侧壁上形成多个第一间隔件，在虚设图案的侧壁上形成多个第二间隔件，以及 移除第二间隔件和心轴图案以在基底上形成多个间隔图案。

公开(公告)号：US09117886B2

公开(公告)日：2015-08-25

申请号：US14091349

申请日：2013-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Jia-Rong Wu ,  Ching-Wen Hung

IPC: H01L21/338 ,  H01L21/44 ,  H01L21/768 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/7827 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for fabricating a semiconductor device is provided according to one embodiment of the present invention and includes forming an interlayer dielectric on a substrate; forming a trench surrounded by the interlayer dielectric; depositing a dielectric layer and a work function layer on a surface of the trench sequentially and conformally; filling up the trench with a conductive layer; removing an upper portion of the conductive layer inside the trench; forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer through a directional deposition process; removing the dielectric layer exposed from the protection film; and forming a hard mask to cover the protection film.

Abstract translation: 根据本发明的一个实施例提供一种制造半导体器件的方法，包括在衬底上形成层间电介质; 形成由层间电介质包围的沟槽; 依次和保形地在沟槽的表面上沉积介电层和功函数层; 用导电层填充沟槽; 去除沟槽内的导电层的上部; 通过定向沉积工艺在层间电介质的顶表面和导电层的顶表面上形成保护膜; 去除从保护膜暴露的电介质层; 并形成硬掩模以覆盖保护膜。

公开(公告)号：US20150145027A1

公开(公告)日：2015-05-28

申请号：US14091349

申请日：2013-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Jia-Rong Wu ,  Ching-Wen Hung

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for fabricating a semiconductor device is provided according to one embodiment of the present invention and includes forming an interlayer dielectric on a substrate; forming a trench surrounded by the interlayer dielectric; depositing a dielectric layer and a work function layer on a surface of the trench sequentially and conformally; filling up the trench with a conductive layer; removing an upper portion of the conductive layer inside the trench; forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer through a directional deposition process; removing the dielectric layer exposed from the protection film; and forming a hard mask to cover the protection film.

Abstract translation: 根据本发明的一个实施例提供一种制造半导体器件的方法，包括在衬底上形成层间电介质; 形成由层间电介质包围的沟槽; 依次和保形地在沟槽的表面上沉积介电层和功函数层; 用导电层填充沟槽; 去除沟槽内的导电层的上部; 通过定向沉积工艺在层间电介质的顶表面和导电层的顶表面上形成保护膜; 去除从保护膜暴露的电介质层; 并形成硬掩模以覆盖保护膜。

公开(公告)号：US20140205953A1

公开(公告)日：2014-07-24

申请号：US13747421

申请日：2013-01-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Po-Chao Tsao ,  Chia-Jui Liang ,  En-Chiuan Liou

IPC: G03F7/20

CPC classification number: H01L21/0274 ,  G03F7/0035 ,  H01L21/0337

Abstract: A method for forming a semiconductor device comprises the following steps: first, a substrate is provided, a first photo-etching process is carried out with a first photomask to form at least one device structure and a plurality of compensation structures, wherein the first photomask comprises at least one device pattern and a plurality of dummy patterns. A photoresist layer is then formed on the device structure and each compensation structures; a second photo-etching process is then carried out with a second photomask to remove each compensation structure.

Abstract translation: 一种用于形成半导体器件的方法包括以下步骤：首先，提供衬底，利用第一光掩模进行第一光蚀刻工艺以形成至少一个器件结构和多个补偿结构，其中第一光掩模 包括至少一个设备图案和多个虚设图案。 然后在器件结构和每个补偿结构上形成光致抗蚀剂层; 然后用第二光掩模执行第二光蚀刻工艺以去除每个补偿结构。

公开(公告)号：US11569133B2

公开(公告)日：2023-01-31

申请号：US16859959

申请日：2020-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

公开(公告)号：US10892194B2

公开(公告)日：2021-01-12

申请号：US16914483

申请日：2020-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Ching-Ling Lin ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Wen-An Liang ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Yuan-Yu Chung ,  I-Ming Tseng

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.

公开(公告)号：US20200176331A1

公开(公告)日：2020-06-04

申请号：US16782083

申请日：2020-02-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Ching-Ling Lin ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Wen-An Liang ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Yuan-Yu Chung ,  I-Ming Tseng

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.