公开(公告)号：US20250079363A1

公开(公告)日：2025-03-06

申请号：US18951546

申请日：2024-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Sung Chiang ,  Chia-Wei Liu ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

IPC: H01L23/00 ,  H01L23/488 ,  H01L23/532 ,  H01L25/065

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface. A height of the step-height is smaller than a thickness of the first bonding layer.

公开(公告)号：US20250056859A1

公开(公告)日：2025-02-13

申请号：US18928226

申请日：2024-10-28

Applicant: United Microelectronics Corp.

Inventor： Jia-He Lin ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a plurality of planar transistors, a fin-type field effect transistor and a first nonactive structure. The substrate includes a first region and a second region. The first region includes a plurality of first planar active regions and a nonactive region. The nonactive region is located between or aside the plurality of first planar active regions and includes a second planar active region. The second region has a fin active region. The plurality of planar transistors are located in the plurality of first planar active regions within the first region. The fin-type field effect transistor is located on the fin active region within the second region. The first nonactive structure is located in the nonactive region between the plurality of planar transistors.

公开(公告)号：US20240379451A1

公开(公告)日：2024-11-14

申请号：US18780420

申请日：2024-07-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.

公开(公告)号：US20240347583A1

公开(公告)日：2024-10-17

申请号：US18195905

申请日：2023-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Sheng Yang ,  Yi-Wen Chen ,  Hung-Yi Wu ,  YI CHUEN ENG ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0603 ,  H01L27/0886

Abstract: A semiconductor device includes a substrate having a medium-voltage (MV) region and a logic region, a gate structure on the MV region, a first single diffusion break (SDB) structure and a second SDB structure in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, top surfaces of the first SDB structure and the second SDB structure are coplanar, bottom surfaces of the first SDB structure and the second SDB structure are coplanar, and the first SDB structure and the second SDB structure are made of same material.

公开(公告)号：US12094956B2

公开(公告)日：2024-09-17

申请号：US18206097

申请日：2023-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L21/033 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/06 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/6681 ,  H01L29/7851 ,  H01L29/7856 ,  H01L21/823821 ,  H01L27/1211 ,  H01L2924/1033 ,  H01L2924/10344

Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

公开(公告)号：US20240128127A1

公开(公告)日：2024-04-18

申请号：US18398190

申请日：2023-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-l Fu ,  Chun-ya Chiu ,  Chi-Ting Wu ,  Chin-HUNG Chen ,  Yu-Hsiang Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

公开(公告)号：US20230326806A1

公开(公告)日：2023-10-12

申请号：US18209492

申请日：2023-06-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L29/0649 ,  H01L27/0886

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, a first isolation structure on the SDB structure, a shallow trench isolation (STI) adjacent to the SDB structure, and a second isolation structure on the STI. Preferably, the first isolation structure further includes a cap layer on the SDB structure and a dielectric layer on the cap layer.

公开(公告)号：US11721770B2

公开(公告)日：2023-08-08

申请号：US17476461

申请日：2021-09-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/78696 ,  H01L21/02603 ,  H01L21/30612 ,  H01L21/30625 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/78681

Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.

公开(公告)号：US20230207692A1

公开(公告)日：2023-06-29

申请号：US18116826

申请日：2023-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7816 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/66681 ,  H01L21/2822 ,  H01L21/28211

Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.

公开(公告)号：US11682724B2

公开(公告)日：2023-06-20

申请号：US17406028

申请日：2021-08-18

Applicant: United Microelectronics Corp.

Inventor： Chun-Ya Chiu ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chin-Hung Chen ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/66689

Abstract: A high voltage transistor structure including a substrate, a first drift region, a second drift region, a first cap layer, a second cap layer, a gate structure, a first source and drain region, and a second source and drain region is provided. The first and second drift regions are disposed in the substrate. The first and second cap layers are respectively disposed on the first and second drift regions. The gate structure is disposed on the substrate and located over at least a portion of the first drift region and at least a portion of the second drift region. The first and second source and drain regions are respectively disposed in the first and second drift regions and located on two sides of the gate structure. The size of the first drift region and the size of the second drift region are asymmetric.