中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

76 records (took 0.023 seconds)

    SEMICONDUCTOR DEVICE HAVING STRAINED FIN STRUCTURE AND METHOD OF MAKING THE SAME
    26.
    发明申请
    SEMICONDUCTOR DEVICE HAVING STRAINED FIN STRUCTURE AND METHOD OF MAKING THE SAME 有权
    具有应变熔体结构的半导体器件及其制造方法

    公开(公告)号：US20150348971A1

    公开(公告)日：2015-12-03

    申请号：US14825165

    申请日：2015-08-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165

    CPC classification number: H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

    Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

    Abstract translation: 半导体器件包括半导体衬底，至少第一鳍结构，至少第二鳍结构，第一栅极，第二栅极，第一源极/漏极区域和第二源极/漏极区域。 半导体衬底至少具有第一有源区以配置第一鳍结构和至少第二有源区以配置第二鳍结构。 与第一/第二栅极部分重叠的第一/第二鳍结构具有第一/第二应力，第一应力和第二应力彼此不同。 第一/第二源极/漏极区域设置在第一/第二栅极的两侧的第一/第二鳍结构中。

    METHOD FOR FORMING A FINFET STRUCTURE
    27.
    发明申请
    METHOD FOR FORMING A FINFET STRUCTURE 审中-公开
    形成FINFET结构的方法

    公开(公告)号：US20150132966A1

    公开(公告)日：2015-05-14

    申请号：US14583813

    申请日：2014-12-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hung-Lin Shih ,  Jei-Ming Chen ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Kuan-Hsien Li

    IPC: H01L21/8234 ,  H01L29/40

    CPC classification number: H01L21/30604 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/401

    Abstract: A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.

    Abstract translation: 一种用于形成FinFET结构的方法包括提供衬底，第一区和限定在衬底上的第二区，分别在第一区和第二区内的衬底上设置第一鳍结构和第二鳍结构。 第一氧化物层覆盖第一鳍结构和第二鳍结构。 接下来，依次在基板和第一氧化物层上完全形成第一保护层和第二保护层，去除第一区域内的第二保护层，然后去除第一区域内的第一保护层。 之后，同时除去覆盖第二区域内的第一鳍结构和第二保护层的第一氧化物层，形成第二氧化物层以覆盖第一鳍结构。

    Method of fabricating semiconductor device
    28.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09018087B2

    公开(公告)日：2015-04-28

    申请号：US14013429

    申请日：2013-08-29

    Applicant: United Microelectronics Corp.

    Inventor： Hung-Lin Shih ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu

    IPC: H01L21/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/02

    CPC classification number: H01L21/02164 ,  H01L21/0217 ,  H01L21/30621 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

    Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.

    Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤。 在基板上形成虚拟栅极结构，其中虚拟栅极结构包括虚拟栅极和堆叠的硬掩模，并且堆叠的硬掩模从底部至顶部包括第一硬掩模层和第二硬掩模层。 在虚拟栅极结构的侧壁上形成间隔物。 在基板上形成掩模层。 在掩模层中形成与第二硬掩模层对应的开口。 去除第二个硬掩模层。 去除掩模层。 执行干蚀刻工艺以去除第一硬掩模层，其中干蚀刻工艺使用NF 3和H 2作为蚀刻剂。

    Method of forming opening on semiconductor substrate
    29.
    发明授权
    Method of forming opening on semiconductor substrate 有权
    在半导体衬底上形成开口的方法

    公开(公告)号：US08962486B2

    公开(公告)日：2015-02-24

    申请号：US14142940

    申请日：2013-12-30

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Po-Chun Chen

    IPC: H01L21/311 ,  H01L21/768

    CPC classification number: H01L21/31144 ,  H01L21/76802

    Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.

    Abstract translation: 本发明提供一种在半导体衬底上形成开口的方法。 首先，提供基板。 然后在基板上形成介电层和盖层。 电介质层的厚度和盖层的厚度之比基本上在15和1.5之间。 接下来，在盖层上形成图案化的氮化硼层。 最后，通过使用图案化的硬掩模作为掩模来执行蚀刻工艺，以蚀刻覆盖层和电介质层，以在盖层和电介质层中形成开口。

    Transistor with non-uniform stress layer with stress concentrated regions
    30.
    发明授权
    Transistor with non-uniform stress layer with stress concentrated regions 有权
    具有应力集中区域的不均匀应力层的晶体管

    公开(公告)号：US08937369B2

    公开(公告)日：2015-01-20

    申请号：US13633094

    申请日：2012-10-01

    Applicant: United Microelectronics Corp.

    Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Yu-Shu Lin ,  Jei-Ming Chen ,  Wen-Yi Teng

    IPC: H01L23/58 ,  H01L21/469

    CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653

    Abstract: A transistor includes a semiconductor substrate, at least a gate structure, at least a first tensile stress layer, a second tensile stress layer, a source region, and a drain region. The gate structure is disposed within a first transistor region of the semiconductor substrate. The first tensile stress layer includes a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition portion between the curved portion and the extension portion. The first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition portion. The second tensile stress layer is disposed on the first tensile stress layer. And the source/drain regions are separately located in the semiconductor substrate on two sides of the gate structure.

    Abstract translation: 晶体管包括半导体衬底，至少栅极结构，至少第一拉伸应力层，第二拉伸应力层，源极区和漏极区。 栅极结构设置在半导体衬底的第一晶体管区域内。 第一拉伸应力层包括包围栅极结构的弯曲部分，至少一个在栅极结构的侧面处位于半导体衬底上的弯曲顶表面的延伸部分和弯曲部分与延伸部分之间的过渡部分。 第一拉伸应力层具有从弯曲部分和延伸部分朝向过渡部分逐渐变薄的厚度。 第二拉伸应力层设置在第一拉伸应力层上。 并且源极/漏极区域分别位于栅极结构两侧的半导体衬底中。

Patent Agency Ranking