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    MICROELECTRONIC PACKAGES HAVING STACKED ACCELEROMETER AND MAGNETOMETER DIE AND METHODS FOR THE PRODUCTION THEREOF
    21.
    发明申请
    MICROELECTRONIC PACKAGES HAVING STACKED ACCELEROMETER AND MAGNETOMETER DIE AND METHODS FOR THE PRODUCTION THEREOF 有权
    具有堆叠加速度计和磁铁计的微电子封装及其生产方法

    公开(公告)号：US20150329352A1

    公开(公告)日：2015-11-19

    申请号：US14806481

    申请日：2015-07-22

    Applicant: FREESCALE SEMICONDUCTOR INC.

    Inventor： PHILIP H. BOWLES ,  STEPHEN R. HOOPER

    IPC: B81B7/00

    CPC classification number: B81B7/0074 ,  B81B7/0041 ,  B81B7/007 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0292 ,  B81B2207/096 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2924/00014

    Abstract: Methods for fabricating multi-sensor microelectronic packages and multi-sensor microelectronic packages are provided. In one embodiment, the method includes positioning a magnetometer wafer comprised of an array of non-singulated magnetometer die over an accelerometer wafer comprised of an array of non-singulated accelerometer die. The magnetometer wafer is bonded to the accelerometer wafer to produce a bonded wafer stack. The bonded wafer stack is then singulated to yield a plurality of multi-sensor microelectronic packages each including a singulated magnetometer die bonded to a singulated accelerometer die.

    Abstract translation: 提供了制造多传感器微电子封装和多传感器微电子封装的方法。 在一个实施例中，该方法包括将由非单一化磁力计阵列阵列组成的磁力计晶片定位在由非单一加速度计模具阵列组成的加速度计晶片上。 磁强计晶片结合到加速度计晶圆上以产生键合晶片叠层。 然后将键合的晶片堆叠单个以产生多个多传感器微电子封装，每个多传感器微电子封装包括结合到单个加速度计管芯的单个磁力计管芯。

    METHOD TO PACKAGE MULTIPLE MEMS SENSORS AND ACTUATORS AT DIFFERENT GASES AND CAVITY PRESSURES
    24.
    发明申请
    METHOD TO PACKAGE MULTIPLE MEMS SENSORS AND ACTUATORS AT DIFFERENT GASES AND CAVITY PRESSURES 有权
    在不同气体和气压下封装多个MEMS传感器和执行器的方法

    公开(公告)号：US20140227816A1

    公开(公告)日：2014-08-14

    申请号：US14102465

    申请日：2013-12-10

    Applicant: mCube Inc.

    Inventor： WENHUA ZHANG ,  Shingo Yoneoka

    IPC: B81C1/00

    CPC classification number: B81B7/02 ,  B81B7/0041 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0292 ,  B81C1/00293 ,  B81C1/00333 ,  B81C2203/0109 ,  B81C2203/0145 ,  B81C2203/0154 ,  H01L21/56 ,  H01L41/1132

    Abstract: A method for fabricating a multiple MEMS device. A semiconductor substrate having a first and second MEMS device, and an encapsulation wafer with a first cavity and a second cavity, which includes at least one channel, can be provided. The first MEMS can be encapsulated within the first cavity and the second MEMS device can be encapsulated within the second cavity. These devices can be encapsulated within a provided first encapsulation environment at a first air pressure, encapsulating the first MEMS device within the first cavity at the first air pressure. The second MEMS device within the second cavity can then be subjected to a provided second encapsulating environment at a second air pressure via the channel of the second cavity.

    Abstract translation: 一种用于制造多个MEMS器件的方法。 可以提供具有第一和第二MEMS器件的半导体衬底以及包括至少一个通道的具有第一腔和第二腔的封装晶片。 第一MEMS可以封装在第一腔内，并且第二MEMS器件可被封装在第二腔内。 这些装置可以以第一空气压力封装在所提供的第一封装环境内，在第一空气压力下将第一MEMS装置封装在第一空腔内。 然后可以在第二空腔内的第二MEMS装置经由第二空腔的通道在第二空气压力下经受所提供的第二封装环境。

    Self-aligned nano-scale device with parallel plate electrodes
    25.
    发明授权
    Self-aligned nano-scale device with parallel plate electrodes 有权
    具有平行平板电极的自对准纳米级装置

    公开(公告)号：US08802990B2

    公开(公告)日：2014-08-12

    申请号：US13432037

    申请日：2012-03-28

    Applicant: Lawrence A. Clevenger ,  Zhengwen Li ,  Kevin S. Petrarca ,  Roger A. Quon ,  Carl J. Radens ,  Brian C. Sapp

    Inventor： Lawrence A. Clevenger ,  Zhengwen Li ,  Kevin S. Petrarca ,  Roger A. Quon ,  Carl J. Radens ,  Brian C. Sapp

    IPC: H01B5/14 ,  H01L21/76 ,  H01L21/764

    CPC classification number: B81C1/00698 ,  B81B2201/0292

    Abstract: A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates.

    Abstract translation: 连续的深沟槽包括在一对第一平行侧壁之间具有恒定宽度的第一沟槽部分，第二沟槽部分和第三沟槽部分各自具有比第一沟槽部分更大的宽度并横向连接到第一沟槽部分。 使用非共形沉积工艺来形成导电层，该导电层在邻接的深沟槽部分内具有锥形几何形状，使得导电层不存在于邻接的深沟槽的底表面上。 形成间隙填充层以堵塞第一沟槽部分中的空间。 将导电层图案化为在第一沟槽部分内具有锥形垂直部分的两个导电板。 在去除间隙填充层的剩余部分之后，形成在导电板的锥形垂直部分之间具有小间隔距离的装置。

    Thermal fluid flow sensor having stacked insulating films above and below heater and temperature-measuring resistive elements
    27.
    发明授权
    Thermal fluid flow sensor having stacked insulating films above and below heater and temperature-measuring resistive elements 有权
    热流体流量传感器在加热器和温度测量电阻元件之上和之下具有堆叠的绝缘膜

    公开(公告)号：US08429964B2

    公开(公告)日：2013-04-30

    申请号：US12633142

    申请日：2009-12-08

    Applicant: Noriyuki Sakuma

    Inventor： Noriyuki Sakuma

    IPC: G01F1/68

    CPC classification number: B81B3/0072 ,  B81B2201/0292 ,  B81B2203/0127 ,  G01F1/6845 ,  G01F1/692 ,  G01F1/699 ,  G01F5/00 ,  Y10T29/49083

    Abstract: A thermal fluid flow sensor having a diaphragm structure body configured by an insulating film formed by stacking a film having compressive stress and a film having tensile stress on the top and bottom of a temperature-measuring resistive element and a heater resistive element which are processed by microprocessing is provided. The insulating film at a lower layer of the heater resistive element, a temperature-measuring resistive element for heater resistive element, upstream temperature-measuring resistive elements, and downstream temperature-measuring resistive elements, has films having compressive stress (a first insulating film, a third insulating film, and a fifth insulating film) and films having tensile stress (a second insulating film and a fourth insulating film) being alternately arranged, and two layers or more of the films having tensile stress are arranged.

    Abstract translation: 一种热流体流量传感器，具有膜结构体，该隔膜结构体由绝缘膜构成，该绝缘膜通过在温度测量电阻元件和加热器电阻元件的顶部和底部堆叠具有压应力的膜和具有拉伸应力的膜而形成， 提供微处理。 加热电阻元件下层的绝缘膜，加热电阻元件的温度测量电阻元件，上游测温电阻元件和下游温度测量电阻元件具有压应力的膜（第一绝缘膜， 第三绝缘膜和第五绝缘膜）和具有拉伸应力的膜（第二绝缘膜和第四绝缘膜）交替布置，并且布置有两层或更多层的具有拉伸应力的膜。

    SENSOR PACKAGE HAVING INTEGRATED ACCELEROMETER AND MAGNETOMETER
    28.
    发明申请
    SENSOR PACKAGE HAVING INTEGRATED ACCELEROMETER AND MAGNETOMETER 审中-公开
    传感器包含集成加速度计和磁力计

    公开(公告)号：US20120255357A1

    公开(公告)日：2012-10-11

    申请号：US13442299

    申请日：2012-04-09

    Applicant: Dongmin Chen ,  Haidong Liu ,  Zhiwei Duan

    Inventor： Dongmin Chen ,  Haidong Liu ,  Zhiwei Duan

    IPC: G01P15/105

    CPC classification number: G01P15/008 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0292 ,  B81B2207/012 ,  G01C25/00

    Abstract: A sensor package has integrated magnetic and acceleration sensor package structures, where a first wafer is bonded to a second wafer with a cavity defined between them. The magnetic sensor is bonded to the bottom of the first wafer and the acceleration sensor is provided within the cavity. Circuitry to drive the accelerometer and interface with the magnetic sensor is provided on the first wafer.

    Abstract translation: 传感器封装具有集成的磁性和加速度传感器封装结构，其中第一晶片与第二晶片结合，其间限定有腔。 磁传感器结合到第一晶片的底部，加速度传感器设置在空腔内。 在第一晶片上提供用于驱动加速度计和与磁传感器接口的电路。

    SELF-ALIGNED NANO-SCALE DEVICE WITH PARALLEL PLATE ELECTRODES
    29.
    发明申请
    SELF-ALIGNED NANO-SCALE DEVICE WITH PARALLEL PLATE ELECTRODES 有权
    具有平行平板电极的自对准纳米尺度装置

    公开(公告)号：US20120189767A1

    公开(公告)日：2012-07-26

    申请号：US13432037

    申请日：2012-03-28

    Applicant: Lawrence A. Clevenger ,  Zhengwen Li ,  Kevin S. Petrarca ,  Roger A. Quon ,  Carl J. Radens ,  Brian C. Sapp

    Inventor： Lawrence A. Clevenger ,  Zhengwen Li ,  Kevin S. Petrarca ,  Roger A. Quon ,  Carl J. Radens ,  Brian C. Sapp

    IPC: B05D5/12 ,  B05D3/00

    CPC classification number: B81C1/00698 ,  B81B2201/0292

    Abstract: A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates.

    Abstract translation: 连续的深沟槽包括在一对第一平行侧壁之间具有恒定宽度的第一沟槽部分，第二沟槽部分和第三沟槽部分各自具有比第一沟槽部分更大的宽度并横向连接到第一沟槽部分。 使用非共形沉积工艺来形成导电层，该导电层在邻接的深沟槽部分内具有锥形几何形状，使得导电层不存在于邻接的深沟槽的底表面上。 形成间隙填充层以堵塞第一沟槽部分中的空间。 将导电层图案化为在第一沟槽部分内具有锥形垂直部分的两个导电板。 在去除间隙填充层的剩余部分之后，形成在导电板的锥形垂直部分之间具有小间隔距离的装置。

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