公开(公告)号：US20120305301A1

公开(公告)日：2012-12-06

申请号：US13399101

申请日：2012-02-17

Applicant: King-Lien Lee

Inventor： King-Lien Lee

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0209 ,  H05K2201/017 ,  H05K2201/0179 ,  H05K2201/10106

Abstract: The invention provides a circuit board with heat sink and a method of fabricating the same. The circuit board according to the invention includes a substrate, a lead layer and a ceramic layer. The lead layer is formed on an upper surface of the substrate, and includes two contact points corresponding to an electronic device. The ceramic layer is formed on the upper surface of the substrate, and particularly formed between such two contact points. The ceramic layer serves as a heat sink for the electronic device.

Abstract translation: 本发明提供一种具有散热器的电路板及其制造方法。 根据本发明的电路板包括基板，引线层和陶瓷层。 引线层形成在基板的上表面上，并且包括对应于电子设备的两个接触点。 陶瓷层形成在基板的上表面上，特别形成在这两个接触点之间。 陶瓷层用作电子设备的散热器。

公开(公告)号：US20120217047A1

公开(公告)日：2012-08-30

申请号：US13407585

申请日：2012-02-28

Applicant: Souhei Kouda ,  Toshiharu Takayama

Inventor： Souhei Kouda ,  Toshiharu Takayama

IPC: H05K1/05

CPC classification number: H05K1/053 ,  H01L23/142 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K3/4685 ,  H05K2201/017 ,  H05K2201/068 ,  H01L2924/00

Abstract: A metal-based circuit board, which reduces the influence of thermal expansion, is provided having a structure where an insulating layer A having a large coefficient of thermal expansion is sandwiched between insulating layers B having a small coefficient of thermal expansion. Such a structure allows the insulating layers B to contract and expand so as to suppress contraction and expansion of the insulating layer A and thereby reduce the stress in the direction of negating the stress. As a result, while warpage or distortion is suppressed to be minimal, the bonding strength of the upper and the lower layer is maintained, and degree of freedom for circuit design is not impaired, thereby providing a highly reliable circuit structure.

Abstract translation: 提供一种减少热膨胀影响的金属基电路板，其具有将具有大的热膨胀系数的绝缘层A夹在具有小的热膨胀系数的绝缘层B之间的结构。 这种结构允许绝缘层B收缩和膨胀，以便抑制绝缘层A的收缩和膨胀，从而减小在否定应力的方向上的应力。 结果，虽然翘曲或变形被抑制到最小，但是上下层的粘合强度得以保持，电路设计的自由度不受损害，从而提供高度可靠的电路结构。

公开(公告)号：US08183108B2

公开(公告)日：2012-05-22

申请号：US12301791

申请日：2006-06-15

Applicant: William J. Borland ,  Seigi Suh ,  Jon-Paul Maria ,  Jon Fredrick Ihlefeld ,  Ian Burn

Inventor： William J. Borland ,  Seigi Suh ,  Jon-Paul Maria ,  Jon Fredrick Ihlefeld ,  Ian Burn

IPC: H01L21/20 ,  H01B3/20 ,  H01B3/00

CPC classification number: H01L21/31691 ,  C23C18/1212 ,  C23C18/1241 ,  C23C18/1266 ,  C23C18/1283 ,  C23C18/1295 ,  H01G4/129 ,  H05K1/162 ,  H05K2201/017 ,  H05K2201/0355

Abstract: A method of making dense dielectrics layers via chemical solution deposition by adding inorganic glass fluxed material to high dielectric constant compositions, depositing the resultant mixture onto a substrate and annealing the substrate at temperatures between the softening point of the inorganic glass flux and the melting point of the substrate. A method of making a capacitor comprising a dense dielectric layer.

Abstract translation: 一种通过在高介电常数组合物中添加无机玻璃助熔材料，通过化学溶液沉积制造致密电介质层的方法，将所得混合物沉积在基材上，并在无机玻璃熔剂的软化点和熔点之间的温度 底物。 一种制造包括致密介电层的电容器的方法。

公开(公告)号：US08134083B2

公开(公告)日：2012-03-13

申请号：US12314086

申请日：2008-12-03

Applicant: Bernd Haegele

Inventor： Bernd Haegele

IPC: H05K1/16

CPC classification number: H05K1/053 ,  C03C3/064 ,  C23C4/18 ,  H05K1/092 ,  H05K2201/0116 ,  H05K2201/017 ,  H05K2201/0179 ,  H05K2203/1147 ,  H05K2203/1366 ,  Y10T29/49126 ,  Y10T29/49146

Abstract: A circuit carrier having a metal support layer, at least some portions of which are covered by a dielectric layer, the dielectric layer having a plurality of pores, with the pores being sealed by glass at least on the opposite side of the dielectric layer to the support layer.

Abstract translation: 一种具有金属支撑层的电路载体，其至少一些部分被电介质层覆盖，所述电介质层具有多个孔，所述电介质层至少在电介质层的相对侧上被玻璃密封， 支持层。

公开(公告)号：US20110266036A1

公开(公告)日：2011-11-03

申请号：US13181572

申请日：2011-07-13

Applicant: Yuichi IIDA ,  Yusuke OTSUKA

Inventor： Yuichi IIDA ,  Yusuke OTSUKA

IPC: H05K1/03 ,  C03B29/00

CPC classification number: H05K1/167 ,  B32B18/00 ,  C04B2235/9607 ,  C04B2237/343 ,  C04B2237/562 ,  C04B2237/62 ,  C04B2237/68 ,  H05K1/0306 ,  H05K3/28 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/017 ,  H05K2203/308

Abstract: A laminate type ceramic electronic component includes a thick film resistor and an overcoat layer so as to prevent defects such as delamination from being caused and to prevent the thick film resistor from being cracked after laser trimming, even when a method is adopted in which an unfired composite laminate is subjected to firing in such a way that an unfired ceramic laminate, an unfired thick film resistor, and an unfired overcoat layer are each integrally sintered. The unfired overcoat layer includes a glass ceramic material containing a ceramic and glass having substantially the same constituents and compositional ratio as those of the glass contained in the unfired ceramic layer. The respective glass ceramic materials constituting the unfired ceramic layer and the unfired overcoat layer are adjusted so that the ratio of a crystalline phase with a smaller coefficient of thermal expansion than the coefficient of thermal expansion of the fired ceramic layer is higher in the overcoat layer than in the ceramic layer.

Abstract translation: 叠层型陶瓷电子部件包括厚膜电阻器和外涂层，以便防止在产生分层之类的缺陷，并且防止厚膜电阻器在激光修整之后破裂，即使采用不熟悉的方法 将复合层叠体进行焙烧，使得未烧结的陶瓷层压体，未烧结的厚膜电阻器和未烧结的外涂层均被一体烧结。 未焙烧的外涂层包括含有陶瓷和玻璃的玻璃陶瓷材料，其具有与未焙烧陶瓷层中所含的玻璃的成分和组成比基本相同的成分和组成比。 调整构成未烧结的陶瓷层和未烧结的外涂层的各玻璃陶瓷材料，使得在外涂层中，具有比煅烧陶瓷层的热膨胀系数小的热膨胀系数的结晶相的比例高于 在陶瓷层中。

公开(公告)号：US07996969B2

公开(公告)日：2011-08-16

申请号：US12181441

申请日：2008-07-29

Applicant: Satoshi Ohaga ,  Yasutaka Sugimoto

Inventor： Satoshi Ohaga ,  Yasutaka Sugimoto

IPC: H01G13/00

CPC classification number: H01G4/105 ,  H01G4/1227 ,  H01G4/30 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/0029 ,  H05K2201/017 ,  H05K2203/171 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49004

Abstract: In a multilayer ceramic substrate having a built-in capacitor provided in a ceramic laminate including a plurality of ceramic layers laminated to each other, the built-in capacitor being formed of a first capacitor electrode, a second capacitor electrode, and one of the dielectric glass ceramic layers, the capacitance value of the built-in capacitor is adjusted by performing laser trimming of the first capacitor electrode. The one dielectric glass ceramic layer is made of a TiO2-based dielectric glass ceramic layer in which the amount of dielectric grains including TiO2 is about 10 percent to about 35 percent by volume.

Abstract translation: 在具有内置电容器的多层陶瓷基板中，所述内置电容器设置在包括彼此层叠的多个陶瓷层的陶瓷层叠体中，所述内置电容器由第一电容器电极，第二电容器电极和所述电介质 玻璃陶瓷层，通过对第一电容器电极进行激光微调来调节内置电容器的电容值。 一个电介质玻璃陶瓷层由TiO 2基电介质玻璃陶瓷层制成，其中包括TiO 2的电介质颗粒的量为约10体积％至约35体积％。

公开(公告)号：US20090205858A1

公开(公告)日：2009-08-20

申请号：US12314086

申请日：2008-12-03

Applicant: Bernd Haegele

Inventor： Bernd Haegele

IPC: H05K1/18 ,  B05D5/12 ,  B05D3/00

CPC classification number: H05K1/053 ,  C03C3/064 ,  C23C4/18 ,  H05K1/092 ,  H05K2201/0116 ,  H05K2201/017 ,  H05K2201/0179 ,  H05K2203/1147 ,  H05K2203/1366 ,  Y10T29/49126 ,  Y10T29/49146

Abstract: Circuit carrier having a metal support layer, at least some portions of which are covered by a dielectric layer, the latter having a plurality of pores, with the pores being sealed by glass at least on the opposite side of the dielectric layer to the support layer.

Abstract translation: 具有金属支撑层的电路载体，其至少一些部分被电介质层覆盖，该电介质层具有多个孔，孔至少在电介质层的与支撑层相反的一侧被玻璃密封 。

公开(公告)号：US07514785B2

公开(公告)日：2009-04-07

申请号：US11337687

申请日：2006-01-24

Applicant: Susumu Toba ,  Akira Morozumi ,  Kazuo Furihata

Inventor： Susumu Toba ,  Akira Morozumi ,  Kazuo Furihata

IPC: H01L23/34

CPC classification number: H05K3/0061 ,  H01L23/373 ,  H01L23/3735 ,  H01L23/5385 ,  H01L25/072 ,  H01L2924/0002 ,  H05K1/142 ,  H05K3/341 ,  H05K3/3452 ,  H05K2201/017 ,  H05K2201/0323 ,  H05K2203/0545 ,  H01L2924/00

Abstract: A semiconductor device includes a solder dam for restricting the flow of solder during manufacturing. The device includes a semiconductor chip bonded to a first side of a circuit board, a metal base for dissipating heat produced by the semiconductor chip, the metal base being bonded to a second side of the circuit board, and a dam material disposed on the metal base in a predetermined pattern for restricting the flow of solder used in bonding a plurality of the circuit boards to the metal base. By employing the solder dam, solderability is not impaired, device contamination can be avoided, and a highly reliable semiconductor device can be produced.

Abstract translation: 半导体器件包括用于在制造期间限制焊料流动的焊料坝。 该装置包括接合到电路板的第一侧的半导体芯片，用于散发由半导体芯片产生的热的金属基底，金属基底接合到电路板的第二侧，以及设置在金属 以预定图案为基础，用于限制将多个电路板接合到金属基底时使用的焊料的流动。 通过使用焊料坝，可焊性不受损害，可以避免器件污染，可以生产高可靠性的半导体器件。

公开(公告)号：US20070003781A1

公开(公告)日：2007-01-04

申请号：US11479159

申请日：2006-06-30

Applicant: L. de Rochemont

Inventor： L. de Rochemont

IPC: B32B15/00

CPC classification number: H01Q9/0414 ,  B82Y30/00 ,  C04B2235/768 ,  C04B2235/781 ,  H01C7/003 ,  H01C17/003 ,  H01C17/06533 ,  H01G4/10 ,  H01G4/1209 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/647 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01025 ,  H01L2924/01037 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q15/0086 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/207 ,  H05K2201/017 ,  H05K2201/0175 ,  H05K2201/09763 ,  H05K2203/016 ,  H05K2203/0338 ,  H05K2203/121 ,  Y10T428/12493

Abstract: An electrical component provides a ceramic element located on or in a dielectric substrate between and in contact with a pair of electrical conductors, wherein the ceramic element includes one or more metal oxides having fluctuations in metal-oxide compositional uniformity less than or equal to 1.5 mol % throughout the ceramic element. A method of fabricating an electrical component, provides or forming a ceramic element between and in contact with a pair of electrical conductors on a substrate including depositing a mixture of metalorganic precursors and causing simultaneous decomposition of the metal oxide precursors to form the ceramic element including one or more metal oxides.

Abstract translation: 电气部件提供位于电介质基板上或介质基板之间的陶瓷元件，其与一对电导体接触并接触，其中陶瓷元件包括一种或多种具有小于或等于1.5摩尔的金属 - 氧化物组成均匀性波动的金属氧化物 ％整个陶瓷元件。 一种制造电气部件的方法，在衬底上提供或形成与一对电导体接触的陶瓷元件，包括沉积金属有机前体的混合物并引起金属氧化物前体的同时分解以形成陶瓷元件，包括一个 或更多的金属氧化物。

公开(公告)号：US20060186520A1

公开(公告)日：2006-08-24

申请号：US11337687

申请日：2006-01-24

Applicant: Susumu Toba ,  Akira Morozumi ,  Kazuo Furihata

Inventor： Susumu Toba ,  Akira Morozumi ,  Kazuo Furihata

IPC: H01L23/02

CPC classification number: H05K3/0061 ,  H01L23/373 ,  H01L23/3735 ,  H01L23/5385 ,  H01L25/072 ,  H01L2924/0002 ,  H05K1/142 ,  H05K3/341 ,  H05K3/3452 ,  H05K2201/017 ,  H05K2201/0323 ,  H05K2203/0545 ,  H01L2924/00

Abstract: A semiconductor device includes a solder dam for restricting the flow of solder during manufacturing. The device includes a semiconductor chip bonded to a first side of a circuit board, a metal base for dissipating heat produced by the semiconductor chip, the metal base being bonded to a second side of the circuit board, and a dam material disposed on the metal base in a predetermined pattern for restricting the flow of solder used in bonding a plurality of the circuit boards to the metal base. By employing the solder dam, solderability is not impaired, device contamination can be avoided, and a highly reliable semiconductor device can be produced.