公开(公告)号：US20150223325A1

公开(公告)日：2015-08-06

申请号：US14612638

申请日：2015-02-03

Applicant: Seiko Epson Corporation

Inventor： Tetsuro MIYAO ,  Hideki ISHIGAMI ,  Yukihiko SHIOHARA ,  Tetsuya OTSUKI ,  Hidefumi NAKAMURA

IPC: H05K1/02 ,  H05K3/40 ,  H05K1/11 ,  H05K1/18 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K1/0271 ,  H01L21/486 ,  H01L23/15 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/1319 ,  H01L2224/16235 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81471 ,  H01L2224/8148 ,  H01L2224/81484 ,  H01L2224/8185 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/16251 ,  H01L2924/164 ,  H05K1/0306 ,  H05K1/09 ,  H05K1/092 ,  H05K1/115 ,  H05K1/184 ,  H05K3/1291 ,  H05K3/4061 ,  H05K2201/0269 ,  H05K2201/0272 ,  H05K2201/10083 ,  H05K2201/1056 ,  H05K2203/1126 ,  H05K2203/1131 ,  H05K2203/1194

Abstract: A base substrate includes a ceramic sintered substrate having through holes, first and second metal wirings which are integrally disposed so as to be connected to the surface of the ceramic sintered substrate and the inside of the through holes, and first and second active metal layers which are disposed between the ceramic sintered substrate and the first and second metal wirings.

Abstract translation: 基底基板包括具有通孔的陶瓷烧结基板，一体地设置成连接到陶瓷烧结基板的表面和通孔内部的第一和第二金属布线以及第一和第二有源金属层， 设置在陶瓷烧结基板和第一和第二金属布线之间。

公开(公告)号：US20140239504A1

公开(公告)日：2014-08-28

申请号：US13779917

申请日：2013-02-28

Applicant: Hwei-Ling Yau ,  David Paul Trauernicht ,  John Andrew Lebens ,  Yongcai Wang ,  Ronald Steven Cok

Inventor： Hwei-Ling Yau ,  David Paul Trauernicht ,  John Andrew Lebens ,  Yongcai Wang ,  Ronald Steven Cok

IPC: H01L33/42

CPC classification number: G01N27/126 ,  G01N27/07 ,  G02F1/13439 ,  G06F3/044 ,  G06F2203/04103 ,  H05K3/0014 ,  H05K3/1258 ,  H05K2201/0108 ,  H05K2201/0112 ,  H05K2201/0257 ,  H05K2201/0269 ,  H05K2201/0272 ,  H05K2201/0338 ,  H05K2201/0376 ,  H05K2201/2054 ,  H05K2203/0108 ,  H05K2203/1131 ,  H05K2203/1476

Abstract: A multi-layer micro-wire structure includes a substrate having a surface. A plurality of micro-channels is formed in the substrate. A first material composition is located in a first layer only in each micro-channel and not on the substrate surface. A second material composition different from the first material composition is located in a second layer different from the first layer only in each micro-channel and not on the substrate surface. The first material composition in the first layer and the second material composition in the second layer form an electrically conductive multi-layer micro-wire in each micro-channel.

Abstract translation: 多层微线结构包括具有表面的基板。 在基板上形成多个微通道。 第一材料组合物仅位于每个微通道中的第一层中，而不位于基底表面上。 不同于第一材料组合物的第二材料组合物仅位于每个微通道而不是在基板表面上的不同于第一层的第二层中。 第一层中的第一材料组合物和第二层中的第二材料组合物在每个微通道中形成导电多层微线。

公开(公告)号：US08747579B2

公开(公告)日：2014-06-10

申请号：US12037958

申请日：2008-02-27

Applicant: Yoshikazu Oshika ,  Munenori Hashimoto ,  Masayuki Nakano

Inventor： Yoshikazu Oshika ,  Munenori Hashimoto ,  Masayuki Nakano

IPC: C22F1/14

CPC classification number: H05K3/3463 ,  H01L24/29 ,  H01L24/33 ,  H01L24/45 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1301 ,  H01L2924/157 ,  H01L2924/15787 ,  H05K2201/0269 ,  H05K2203/1105 ,  H05K2203/1157 ,  Y10T29/49149 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2924/00015

Abstract: A solder layer and an electronic device bonding substrate having high bonding strength of a device and low bonding failure even by a simplified bonding method of a device to a substrate and a method for manufacturing the same are provided.A device bonding substrate 1 including a substrate 2 and a lead free solder layer 5 formed on said substrate has a solder layer 5 consisting of a plurality of layers having mutually different phases, and oxygen concentration on the upper surface of the solder layer is lower than 30 atomic % of the concentration of the metal component which is the most oxidizable among the metal components making up the upper layer of the solder layer 5. Carbon concentration on the upper surface of the solder layer 5 may be lower than 10 atomic % of the concentration of the metal component which is the most oxidizable among the metal components making up the upper layer of the solder layer.

Abstract translation: 提供了一种焊接层和具有高的器件结合强度和低接合故障的电子器件接合衬底，即使通过简化的器件对衬底的接合方法及其制造方法也是如此。 包括形成在所述基板上的基板2和无铅焊料层5的器件接合基板1具有由具有相互不同相的多个层构成的焊料层5，焊料层的上表面的氧浓度低于 在构成焊料层5的上层的金属成分中最可氧化的金属成分的浓度的30原子％。焊料层5的上表面的碳浓度可以低于焊料层5的10原子％ 在构成焊料层的上层的金属成分中最可氧化的金属成分的浓度。

公开(公告)号：US20120301824A1

公开(公告)日：2012-11-29

申请号：US13569375

申请日：2012-08-08

Applicant: Takahiro YOSHIDA ,  Shouji Minegishi ,  Masao Arima

Inventor： Takahiro YOSHIDA ,  Shouji Minegishi ,  Masao Arima

IPC: G03F7/004

CPC classification number: G03F7/095 ,  G03F7/004 ,  G03F7/0047 ,  H05K3/285 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068

Abstract: In a layered structure having at least a substrate and a photosensitive resin layer or cured film layer formed on the substrate and containing an inorganic filler, the content of the inorganic filler in the photosensitive resin layer or cured film layer is low on the side contacting the substrate and high on the surface side away from the substrate, so that a linear thermal expansion coefficient of the photosensitive resin layer or cured film layer as a whole is maintained as low as possible. Preferably, the inorganic filler content in the layer gradually increases continuously obliquely or stepwise from the side contacting the substrate to the surface side away from the substrate. A photosensitive dry film containing the above-mentioned photosensitive resin layer is suitable for use as a solder resist or an interlayer resin insulation layer of a printed wiring board.

Abstract translation: 在至少具有基板和形成在基板上并含有无机填料的感光性树脂层或固化膜层的分层结构中，感光性树脂层或固化膜层中的无机填料的含量在与 基板，并且远离基板的表面侧高，使得整个感光性树脂层或固化膜层的线性热膨胀系数保持尽可能低。 优选地，层中的无机填料含量从接触基板的表面侧离开基板的角度或逐步地逐渐增加。 含有上述感光性树脂层的感光性干膜适合用作印刷电路板的阻焊剂或层间树脂绝缘层。

公开(公告)号：US08319108B2

公开(公告)日：2012-11-27

申请号：US12535760

申请日：2009-08-05

Applicant: Atsushi Yamaguchi ,  Koso Matsuno ,  Ryo Kuwabara ,  Hiroe Kowada ,  Kimiaki Nakaya

Inventor： Atsushi Yamaguchi ,  Koso Matsuno ,  Ryo Kuwabara ,  Hiroe Kowada ,  Kimiaki Nakaya

IPC: H05K7/20

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/75 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/351 ,  H05K1/0203 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T428/24372 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A mounting structure formed by bonding the electrodes of a substantially planar electronic component to the electrodes provided on the mounting surface of a circuit board includes a sealing body 5 formed between one main surface of the electronic component and the circuit board and/or on the other main surface of the electronic component. The sealing body 5 is composed of a plurality of layers having different adhesive strengths and thermal conductivities, wherein a layer having a relatively high adhesion strength is arranged in a region being in contact with either one of the electronic component and the circuit board, and a layer having a relatively high thermal conductivity is arranged in a region being in contact with none of the electronic component and the circuit board.

Abstract translation: 通过将基本上平面的电子部件的电极接合到设置在电路基板的安装面上的电极而形成的安装结构包括形成在电子部件的一个主面和电路基板之间和/或另一个之间的密封体5 电子元件的主表面。 密封体5由具有不同粘合强度和导热性的多个层组成，其中具有相对较高粘合强度的层被布置在与电子部件和电路板中的任一个接触的区域中，并且 在与电子部件和电路基板没有接触的区域中布置具有较高热传导率的层。

公开(公告)号：US08207452B2

公开(公告)日：2012-06-26

申请号：US12466604

申请日：2009-05-15

Applicant: Issey Yamamoto ,  Akihiko Kamada

Inventor： Issey Yamamoto ,  Akihiko Kamada

IPC: H05K1/11

CPC classification number: H05K1/0271 ,  H05K1/0306 ,  H05K3/12 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0269 ,  H05K2201/09781

Abstract: A multilayer interconnection board includes a plurality of laminated ceramic layers. Wiring electrodes are disposed on principal surfaces of the ceramic layers, and dot patterns are arranged around the wiring electrodes. The dot patterns are arranged such that the density distribution thereof is varied such that the ratio of the presence of the dot patterns in the vicinity of the wiring electrode is relatively large and the ratio of the presence is reduced as the distance from the wiring electrode increases.

Abstract translation: 多层互连板包括多个层压陶瓷层。 布线电极设置在陶瓷层的主表面上，并且点阵图形布置在布线电极周围。 点图案被布置为使得其密度分布变化，使得布线电极附近的点图案的存在比例相对较大，并且随着与布线电极的距离增加而存在的比例降低 。

公开(公告)号：US08198540B2

公开(公告)日：2012-06-12

申请号：US12303513

申请日：2007-06-06

Applicant: Yoshirou Kuromitsu ,  Hiroya Ishizuka ,  Hiroshi Miyata ,  Takeshi Kitahara ,  Hiroshi Tonomura

Inventor： Yoshirou Kuromitsu ,  Hiroya Ishizuka ,  Hiroshi Miyata ,  Takeshi Kitahara ,  Hiroshi Tonomura

IPC: H05K1/00 ,  H05K7/20

CPC classification number: H01L23/3736 ,  H01L23/3735 ,  H01L23/473 ,  H01L24/32 ,  H01L2224/32225 ,  H05K1/09 ,  H05K3/38 ,  H05K2201/0269 ,  Y10T29/49124

Abstract: A power element mounting substrate including a circuit layer brazed to a surface of a ceramic plate, and a power element soldered to a front surface of the circuit layer, wherein the circuit layer is constituted using an Al alloy with an average purity of more than or equal to 98.0 wt % and less than or equal to 99.9 wt %, Fe concentration of the circuit layer at a side of a surface to be brazed to the ceramic plate is less than 0.1 wt %, and Fe concentration of the circuit layer at a side of the surface opposite to the surface to be brazed is more than or equal to 0.1 wt %.

Abstract translation: 一种功率元件安装基板，包括钎焊到陶瓷板的表面的电路层和焊接到电路层的前表面的功率元件，其中电路层使用平均纯度大于或等于 等于98.0重量％且小于或等于99.9重量％时，要钎焊到陶瓷板的表面侧的电路层的Fe浓度小于0.1重量％，电路层的铁浓度在 与钎焊表面相对的表面的一侧大于或等于0.1重量％。

公开(公告)号：US08168288B2

公开(公告)日：2012-05-01

申请号：US12548661

申请日：2009-08-27

Applicant: Masato Nomiya ,  Satoshi Asakura ,  Tatsuya Ueda ,  Akira Baba

Inventor： Masato Nomiya ,  Satoshi Asakura ,  Tatsuya Ueda ,  Akira Baba

IPC: H05K1/11 ,  B32B17/06 ,  B22F3/10 ,  C04B35/64

CPC classification number: H05K3/38 ,  B32B18/00 ,  C04B2235/36 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/345 ,  C04B2237/346 ,  C04B2237/348 ,  C04B2237/62 ,  C04B2237/68 ,  C04B2237/704 ,  H05K1/0306 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4688 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0269 ,  Y10T428/12056 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: In a multilayer ceramic substrate manufactured by a non-shrinking process, a bonding strength of an external conductive film formed on a primary surface of the multilayer ceramic substrate is increased. After a laminate of a multilayer ceramic substrate is formed from first ceramic layers and second shrinkage suppressing ceramic layers, and an underlayer is formed along one primary surface of the multilayer ceramic substrate, an external conductive film is formed on the underlayer. A non-sintering ceramic material powder in a non-sintered state is included in both the external conductive film and the underlayer, and this non-sintering ceramic material powder is fixed due to diffusion of a glass component from the first ceramic layers.

Abstract translation: 在通过非收缩工艺制造的多层陶瓷基板中，形成在多层陶瓷基板的主表面上的外部导电膜的接合强度增加。 在由第一陶瓷层和第二收缩抑制陶瓷层形成多层陶瓷基板的层压体之后，沿着多层陶瓷基板的一个主面形成下层，在底层上形成外部导电膜。 外部导电膜和底层都包含非烧结状态的非烧结陶瓷材料粉末，由于来自第一陶瓷层的玻璃成分的扩散，这种非烧结陶瓷材料粉末被固定。

公开(公告)号：US08154123B2

公开(公告)日：2012-04-10

申请号：US12707872

申请日：2010-02-18

Applicant: Shigeru Kondou ,  Yoshihiro Tomura

Inventor： Shigeru Kondou ,  Yoshihiro Tomura

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81204 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/014 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068 ,  H05K2203/0292 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/207

Abstract: A solder bump and a conductive connection structure are provided which can conductively connect a semiconductor chip and a substrate with high connection reliability. Filler 5 is contained in a solder bump 6 and a solder joint 17 which connect a connection electrode 3 of a semiconductor chip 2 and a substrate 11, and the filler has a larger density on the side of the connection electrode 3 than on the side of the substrate 11 in the solder joint 17. Therefore, in the cooling solidification of solder, the shrinkage of the solder joint 17 near the connection electrode 3 of the semiconductor chip 2 is reduced by the filler 5 and the occurrence of a stress is reduced on the peripheral portion of the connection electrode 3, thereby preventing the occurrence of cracks near the joint.

Abstract translation: 提供了一种焊料凸块和导电连接结构，其可以以高连接可靠性导电地连接半导体芯片和基板。 填料5包含在焊料凸块6和连接半导体芯片2的连接电极3和基板11的焊接接头17上，并且填料在连接电极3的一侧具有比在侧面 因此，在焊料的冷却固化中，通过填料5减少了半导体芯片2的连接电极3附近的焊料接合部17的收缩，并且减少了应力的发生 连接电极3的周边部分，从而防止在接头附近发生裂纹。

公开(公告)号：US20100213609A1

公开(公告)日：2010-08-26

申请号：US12707872

申请日：2010-02-18

Applicant: Shigeru Kondou ,  Yoshihiro Tomura

Inventor： Shigeru Kondou ,  Yoshihiro Tomura

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81204 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/014 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/0209 ,  H05K2201/0269 ,  H05K2201/068 ,  H05K2203/0292 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/207

Abstract: A solder bump and a conductive connection structure are provided which can conductively connect a semiconductor chip and a substrate with high connection reliability. Filler 5 is contained in a solder bump 6 and a solder joint 17 which connect a connection electrode 3 of a semiconductor chip 2 and a substrate 11, and the filler has a larger density on the side of the connection electrode 3 than on the side of the substrate 11 in the solder joint 17. Therefore, in the cooling solidification of solder, the shrinkage of the solder joint 17 near the connection electrode 3 of the semiconductor chip 2 is reduced by the filler 5 and the occurrence of a stress is reduced on the peripheral portion of the connection electrode 3, thereby preventing the occurrence of cracks near the joint.

Abstract translation: 提供了一种焊料凸块和导电连接结构，其可以以高连接可靠性导电地连接半导体芯片和基板。 填料5包含在焊料凸块6和连接半导体芯片2的连接电极3和基板11的焊接接头17上，并且填料在连接电极3的一侧具有比在侧面 因此，在焊料的冷却固化中，通过填料5减少了半导体芯片2的连接电极3附近的焊料接合部17的收缩，并且减少了应力的发生 连接电极3的周边部分，从而防止在接头附近发生裂纹。