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公开(公告)号:US09907164B2
公开(公告)日:2018-02-27
申请号:US13997569
申请日:2011-12-23
Applicant: Sang Myung Lee , Sung Woon Yoon , Hyuk Soo Lee , Sung Won Lee , Ki Do Chun
Inventor: Sang Myung Lee , Sung Woon Yoon , Hyuk Soo Lee , Sung Won Lee , Ki Do Chun
CPC classification number: H05K1/0298 , H05K3/46 , H05K3/4647 , H05K3/465 , H05K3/4652 , H05K3/4682 , H05K2201/0338 , H05K2203/0376
Abstract: Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer. The via includes a first part, a second part below the first part, and a third part between the first and second parts, and the third part includes a metal different from a metal of the first and second parts. The inner circuit layer and the via are simultaneously formed.
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22.
公开(公告)号:US09905708B2
公开(公告)日:2018-02-27
申请号:US13911974
申请日:2013-06-06
Applicant: Jun Sakamoto
Inventor: Koji Sakamoto
IPC: H01L31/0224 , H01L31/18 , B41F9/06 , B41F13/008 , B41F17/24 , H05K3/12 , H05K1/02 , H05K1/09 , H05K3/40 , B05C1/08
CPC classification number: H01L31/022425 , B05C1/0813 , B05C1/0817 , B41F9/063 , B41F13/008 , B41F17/24 , B41J2202/04 , H01L31/022466 , H01L31/1884 , H05K1/0289 , H05K1/092 , H05K3/1241 , H05K3/4007 , H05K2201/0108 , H05K2201/0338 , H05K2203/1476 , H05K2203/1545 , Y02E10/50
Abstract: A panel of the present invention includes a substrate, an electrode provided on the substrate, and a transparent conductive layer provided on the substrate along a side of the electrode. The electrode includes a contact region in contact with the transparent conductive layer and a non-contact region out of contact with the transparent conductive layer. Preferably, a part of the electrode is exposed through the transparent conductive layer. Preferably, the conductive layer is separated into one side and the other side of the electrode extending a predetermined direction.
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公开(公告)号:US20180054890A1
公开(公告)日:2018-02-22
申请号:US15682721
申请日:2017-08-22
Applicant: IBIDEN CO., LTD.
Inventor: Teruyuki ISHIHARA , Hiroyuki BAN , Haiying MEI
CPC classification number: H05K1/113 , H05K1/0298 , H05K1/0313 , H05K1/181 , H05K3/025 , H05K3/06 , H05K3/243 , H05K3/284 , H05K3/3436 , H05K3/4007 , H05K3/465 , H05K3/4682 , H05K2201/0338 , H05K2201/10378 , Y02P70/611
Abstract: A printed wiring board includes a support plate, a laminate formed on the support plate and including first conductor pads on first surface side of the laminate and first via conductors on second surface side of the laminate, and a solder resist layer interposed between the plate and the laminate and having openings formed such that the openings are exposing the first pads. The laminate has first surface on the first surface side and second surface on the second surface side on the opposite side and includes a first resin insulating layer forming the second surface of the laminate, and the first conductors are formed through the first insulating layer such that the first vias are tapering from the first surface side toward the second surface side of the laminate and have end surfaces recessed from the second surface of the laminate on the second surface side of the laminate.
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公开(公告)号:US09900979B2
公开(公告)日:2018-02-20
申请号:US15240132
申请日:2016-08-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hiesang Sohn , Chan Kwak , Mi Jeong Kim , Hyeon Cheol Park , Weonho Shin , Youngjin Cho
CPC classification number: H05K1/09 , C01B31/0484 , C01B32/184 , H05K1/0306 , H05K1/0313 , H05K3/146 , H05K3/22 , H05K2201/0145 , H05K2201/0154 , H05K2201/0158 , H05K2201/0323 , H05K2201/0338 , H05K2203/0783 , Y02E10/50
Abstract: A conductor includes a substrate, a first conductive layer disposed on the substrate and including two or more islands including graphene, and a second conductive layer disposed on the first conductive layer and including a conductive metal nanowire, wherein at least one of an upper surface and a lower surface of the islands including graphene includes a P-type dopant.
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公开(公告)号:US09888619B2
公开(公告)日:2018-02-06
申请号:US14414514
申请日:2013-06-05
Applicant: TATSUTA ELECTRIC WIRE & CABLE CO., LTD.
Inventor: Yusuke Haruna , Sirou Yamauchi , Hiroshi Tajima , Kenji Kamino
CPC classification number: H05K9/0088 , B32B7/12 , B32B15/04 , B32B15/20 , B32B2307/202 , B32B2307/206 , B32B2457/00 , H05K1/0215 , H05K1/0216 , H05K1/0218 , H05K1/0296 , H05K2201/0154 , H05K2201/0338 , H05K2201/0347 , H05K2201/0355 , H05K2201/0707 , H05K2201/0715 , H05K2203/072 , H05K2203/0723
Abstract: Provided are: a shield film having excellent shield characteristics in the high frequency region of the shield film; and a shield printed wiring board. A shield film (1) is provided on a flexible printed wiring board (8), which has a base film (5) having a signal circuit (6a) formed thereon, and an insulating film (7) that is provided on the whole upper surface of the base film (5) such that the insulating film covers the signal circuit (6a). The shield film 1 has an electroconductive adhesive layer 15 provided throughout a surface of the insulating film 7, and a metal layer 11 provided throughout a surface of the electroconductive adhesive layer 15.
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公开(公告)号:US20170367191A1
公开(公告)日:2017-12-21
申请号:US15691313
申请日:2017-08-30
Applicant: Avary Holding (Shenzhen) Co., Limited. , HongQiSheng Precision Electronics (QinHuangDao) Co ., Ltd. , GARUDA TECHNOLOGY CO., LTD
Inventor: WEI-SHUO SU
CPC classification number: H05K3/244 , H05K3/108 , H05K3/427 , H05K2201/0154 , H05K2201/0338 , H05K2201/09736 , H05K2201/098 , H05K2203/0723 , H05K2203/1394
Abstract: A printed circuit board includes a base layer, a first conductive pattern, and a first surface treatment patterned layer formed on a portion of a surface of the first conductive pattern. The first conductive pattern includes a first copper foil layer on one side of the base layer and a first conductive layer on a portion of a surface of the first copper foil layer. The first conductive pattern which is covered by the first surface treatment patterned layer has sidewalls obliquely tilted with respect to the base layer. The first conductive pattern covered with the first surface treatment patterned layer has a cross section that is trapezoidal shaped, and a width which gradually decreases from the base layer to the first conductive layer.
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公开(公告)号:US09842669B2
公开(公告)日:2017-12-12
申请号:US15220866
申请日:2016-07-27
Inventor: Chan Woo Park , Jae Bon Koo , Bock Soon Na , Rae-Man Park , Ji-Young Oh , Sang Seok Lee , Soon-Won Jung
IPC: H01B7/00 , H01B7/06 , H01B13/008 , H05K1/02
CPC classification number: H01B7/06 , H01B13/008 , H05K1/0283 , H05K3/007 , H05K3/107 , H05K3/20 , H05K2201/0329 , H05K2201/0338 , H05K2201/035 , H05K2203/016 , H05K2203/0568 , H05K2203/128
Abstract: A stretchable wire including a stretchable solid-phase conductive structure; a stretchable insulation layer which surrounds the solid-phase conductive structure; and a liquid-phase conductive material layer disposed between the solid-phase conductive structure and the stretchable insulation layer, and in contact with the solid-phase conductive structure, and a method of fabricating the same.
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公开(公告)号:US09832856B2
公开(公告)日:2017-11-28
申请号:US15002720
申请日:2016-01-21
Applicant: Samsung Electro-Mechanics Co., Ltd.
Inventor: Tae-Hong Min , Myung-Sam Kang , Young-Gwan Ko
CPC classification number: H05K1/0204 , H05K1/0207 , H05K1/0218 , H05K1/0271 , H05K3/4608 , H05K2201/0323 , H05K2201/0338 , H05K2201/066 , H05K2201/10416
Abstract: Disclosed are a circuit board and a method of manufacturing the same. The circuit board includes an insulating part, a heat-transfer body disposed in the insulating part, the heat-transfer body including a thermally conductive material formed in a column shape, and a function hole penetrating the heat-transfer body between a top surface and a bottom surface of the heat-transfer body.
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公开(公告)号:US09826635B2
公开(公告)日:2017-11-21
申请号:US14556407
申请日:2014-12-01
Applicant: JX Nippon Mining & Metals Corporation
Inventor: Tomota Nagaura , Kazuhiko Sakaguchi
IPC: B32B15/00 , H05K1/09 , B32B15/01 , C25D1/04 , C25D3/04 , C25D3/12 , C25D5/14 , C25D7/06 , C25D9/08 , C23C28/02 , C23C18/31 , C25D3/38 , C25D3/58 , C25D3/14 , C25D3/16 , C25D3/56 , C25D11/38 , C23C18/16 , H05K3/02
CPC classification number: H05K1/09 , B32B15/01 , C23C18/165 , C23C18/31 , C23C28/023 , C25D1/04 , C25D3/04 , C25D3/12 , C25D3/14 , C25D3/16 , C25D3/38 , C25D3/562 , C25D3/565 , C25D3/58 , C25D5/14 , C25D7/0614 , C25D9/08 , C25D11/38 , H05K3/025 , H05K2201/0317 , H05K2201/032 , H05K2201/0338 , H05K2201/0355 , H05K2203/0307 , Y10T428/12438 , Y10T428/12493 , Y10T428/12514 , Y10T428/12611 , Y10T428/12667 , Y10T428/12861 , Y10T428/12882 , Y10T428/1291 , Y10T428/12931 , Y10T428/12944 , Y10T428/12958 , Y10T428/24917
Abstract: The present invention provides a carrier-attached copper foil, wherein an ultrathin copper foil is not peeled from the carrier prior to the lamination to an insulating substrate, but can be peeled from the carrier after the lamination to the insulating substrate. A carrier-attached copper foil comprising a copper foil carrier, an intermediate layer laminated on the copper foil carrier, and an ultrathin copper layer laminated on the intermediate layer, wherein the intermediate foil is configured with a Ni layer in contact with an interface of the copper foil carrier and a Cr layer in contact with an interface of the ultrathin copper layer, said Ni layer containing 1,000-40,000 μg/dm2 of Ni and said Cr layer containing 10-100 μg/dm2 of Cr is provided.
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公开(公告)号:US09814137B2
公开(公告)日:2017-11-07
申请号:US15135638
申请日:2016-04-22
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Ryota Asai
CPC classification number: H05K1/115 , H05K1/0298 , H05K1/0306 , H05K1/038 , H05K1/09 , H05K3/108 , H05K3/244 , H05K3/28 , H05K2201/0145 , H05K2201/0195 , H05K2201/0338 , H05K2201/0391 , H05K2201/099 , H05K2201/09909
Abstract: A wiring board is provided with: an insulating layer; a base electrode layer layered on one primary surface of the insulating layer in predetermined regions; an insulating covering layer layered on one primary surface of the insulating layer in a state covering parts of edges of the base electrode layer; and a surface electrode layer plated on exposed portions of the base electrode layer not covered by the insulating covering layer, the thickness of covered portions of the base electrode layer covered by the insulating covering layer being less than the thickness of the exposed portions. The surface electrode layer is formed only on the exposed portions of the base electrode layer.
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