公开(公告)号：US09730332B2

公开(公告)日：2017-08-08

申请号：US14342288

申请日：2013-11-11

Applicant: JX Nippon Mining & Metals Corporation

Inventor： Hideta Arai ,  Atsushi Miki ,  Kohsuke Arai ,  Kaichiro Nakamuro

IPC: B32B15/01 ,  H05K1/05 ,  C25D1/04 ,  H05K3/02 ,  H05K1/03 ,  H05K1/09 ,  H05K3/36 ,  H05K1/14 ,  H05K1/02

CPC classification number: H05K3/022 ,  C25D1/04 ,  C25D7/0614 ,  H05K1/028 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/14 ,  H05K3/361 ,  H05K3/384 ,  H05K2201/0154 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/05 ,  H05K2201/058 ,  Y10T29/49126 ,  Y10T428/12431 ,  Y10T428/24917 ,  Y10T428/31681

Abstract: A surface treated copper foil which is well bonded to a resin and achieves excellent visibility when observed through the resin, and a laminate using the same are provided. The surface treated copper foil to be laminated on a polyimide having the following ΔB (PI) of 50 or more and 65 or less before being laminated to the copper foil so as to form a copper clad laminate comprising a surface having a color difference ΔE*ab of 50 or more based on JIS Z 8730 through the polyimide and a difference between the top average Bt and the bottom average Bb in a brightness curve extending from an edge of the copper foil to a portion without the copper foil ΔB (ΔB=Bt−Bb) of 40 or more, wherein the brightness curve is obtained from an observation spot versus brightness graph of measurement results of the brightness of the photographed image of the copper foil through the polyimide laminated from the surface treated surface side with a CCD camera for the respective observation spots along the perpendicular direction of the extending direction of the observed copper foil.

公开(公告)号：US20170208680A1

公开(公告)日：2017-07-20

申请号：US15404351

申请日：2017-01-12

Applicant: JX Nippon Mining & Metals Corporation

Inventor： Ryo Fukuchi

IPC: H05K1/02 ,  H05K3/20 ,  H01Q1/38 ,  H05K3/06 ,  H05K1/03 ,  H05K1/09 ,  H05K3/38 ,  H05K3/02

CPC classification number: H05K1/0237 ,  C22C9/00 ,  C22C9/02 ,  H01Q1/38 ,  H05K1/0313 ,  H05K1/09 ,  H05K3/022 ,  H05K3/06 ,  H05K3/202 ,  H05K3/389 ,  H05K2201/0141 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2203/0307

Abstract: To provide a copper foil and a copper-clad laminate board that have a good circuit formability and have a favorably suppressed transmission loss even in the use thereof in a high frequency circuit board. A copper foil comprising a gloss face, a surface roughness Ra of a surface of the copper foil on the gloss face side being 0.25 μm or less measured with a laser microscope and a surface roughness Rz of the surface of the copper foil on the gloss face side being 1.10 μm or less measured with a laser microscope, wherein the copper foil has a layer structure after heating at 200° C. for 30 minutes or after heating at 130° C. for 30 minutes or after heating at 300° C. for 30 minutes.

公开(公告)号：US20170196083A1

公开(公告)日：2017-07-06

申请号：US15398126

申请日：2017-01-04

Applicant: JX Nippon Mining & Metals Corporation

Inventor： Atsushi Miki ,  Ryo Fukuchi ,  Hideta Arai

IPC: H05K1/09 ,  C22C30/02 ,  C25F1/00 ,  C25D3/38 ,  C25D3/12 ,  C23C14/16 ,  C25D7/06 ,  C22F1/08 ,  C23C14/06 ,  C23C14/34 ,  C23C14/02 ,  C22C9/00 ,  C25D11/38

CPC classification number: H05K1/09 ,  C22C9/00 ,  C22C30/02 ,  C22F1/08 ,  C25D3/12 ,  C25D3/38 ,  C25D3/562 ,  C25D3/565 ,  C25D3/58 ,  C25D5/12 ,  C25D7/0614 ,  C25D11/38 ,  C25F1/00 ,  H05K3/382 ,  H05K3/389 ,  H05K2201/0355

Abstract: To provide a surface-treated copper foil that is excellent in adhesiveness to an insulating substrate at ordinary temperature, and is capable of suppressing the formation of blister on application of a thermal load of reflow soldering to a copper-clad laminate board constituted by the copper foil. A surface-treated copper foil having a surface-treated surface, the surface-treated copper foil satisfying one or more of the following conditions (1) to (3): by an XPS measurement at a depth after sputtering from the surface-treated surface for 0.5 min at a rate of 1.1 nm/min (SiO2 conversion), (1) the N concentration is from 1.5 to 7.5 atomic %; (2) the C concentration is from 12 to 30 atomic %; and (3) the Si concentration is 3.1 atomic % or more and the O concentration is from 40 to 48 atomic %.

公开(公告)号：US09622354B2

公开(公告)日：2017-04-11

申请号：US14076292

申请日：2013-11-11

Applicant: GE Embedded Electronics Oy

Inventor： Risto Tuominen ,  Antti Iihola ,  Petteri Palm

IPC: H05K3/30 ,  H05K3/06 ,  H01L21/48 ,  H01L23/13 ,  H05K1/18 ,  H01L23/538 ,  H01L23/544 ,  H01L23/00 ,  H05K3/20 ,  H05K3/28 ,  H05K3/32 ,  H05K3/40

CPC classification number: H05K3/064 ,  H01L21/4846 ,  H01L21/56 ,  H01L21/568 ,  H01L23/13 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/16 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/90 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/04105 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/24227 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81121 ,  H01L2224/81132 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/92144 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/183 ,  H05K1/187 ,  H05K1/188 ,  H05K3/205 ,  H05K3/284 ,  H05K3/303 ,  H05K3/305 ,  H05K3/32 ,  H05K3/321 ,  H05K3/4069 ,  H05K2201/0355 ,  H05K2201/09563 ,  H05K2201/0969 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/0353 ,  H05K2203/063 ,  H05K2203/0723 ,  Y02P70/613 ,  Y10T29/4913 ,  H01L2224/29075 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method for manufacturing a circuit-board structure wherein a conductor foil is provided on an insulating material layer, a resist layer is spread on the conductor foil and a recess formed in the conductor foil and insulating material layer. The resist layer is patterned to form a conductor-pattern having openings wherein conductor patterns may be grown. A component is attached to the conductor foil and conductor pattern and conductor material is removed which does not form part of a conductor pattern.

公开(公告)号：US20170094787A1

公开(公告)日：2017-03-30

申请号：US15255899

申请日：2016-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-yong JOO ,  Jin-hyung LEE

IPC: H05K1/03 ,  H05K1/09 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0366 ,  H05K1/0257 ,  H05K1/0298 ,  H05K1/038 ,  H05K1/09 ,  H05K1/181 ,  H05K3/4617 ,  H05K2201/0104 ,  H05K2201/0284 ,  H05K2201/0355 ,  H05K2203/0278

Abstract: Disclosed is a printed circuit board, to which at least one circuit device is mountable, including a base layer with a plurality of paper layers; a waterproof insulation layer laid on a first surface of the base layer; a copper foil layer laid on a second surface opposite to the first surface of the base layer and printed with a signal line pattern connectable with the at least one circuit device; and an adhesive layer configured to be interposed between the base layer and the copper foil layer that includes an adhesive material for adhering the base layer and the copper foil layer.

公开(公告)号：US20170079131A1

公开(公告)日：2017-03-16

申请号：US14855635

申请日：2015-09-16

Applicant: International Business Machines Corporation

Inventor： Brian L. Carlson ,  John R. Dangler ,  Roger S. Krabbenhoft ,  Kevin A. Splittstoesser

IPC: H05K1/02 ,  H05K3/06

CPC classification number: H05K3/26 ,  H01P3/02 ,  H05K1/0213 ,  H05K1/0237 ,  H05K1/0242 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/09 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K3/06 ,  H05K3/064 ,  H05K3/382 ,  H05K3/46 ,  H05K3/4611 ,  H05K2201/0355 ,  H05K2201/0391 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A circuit apparatuses include at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.

Abstract translation: 电路装置包括由图案化导电片形成的至少一个电路特征。 导电片包括不规则表面和平坦化表面。 电路装置的第一区域的导电片粗糙度最小化，并保持在电路装置的第二区域。 选择性地平坦化导电片的部分允许利用较低成本的较粗糙的导电片。 平坦化表面允许增加的信号完整性和降低的插入损耗，并且不规则表面允许增加电路装置的粘附性和增强可靠性。

公开(公告)号：US20170042044A1

公开(公告)日：2017-02-09

申请号：US15229203

申请日：2016-08-05

Applicant: JX Nippon Mining & Metals Corporation

Inventor： Nobuaki Miyamoto

IPC: H05K3/46 ,  H05K3/02 ,  H05K1/09

CPC classification number: H05K3/4682 ,  H05K1/09 ,  H05K3/0035 ,  H05K3/007 ,  H05K3/025 ,  H05K3/108 ,  H05K3/4611 ,  H05K3/4661 ,  H05K2201/0355 ,  H05K2203/0307 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/06

Abstract: Provided herein is a carrier-attached copper foil having desirable fine circuit formability. The carrier-attached copper foil includes a carrier, an interlayer, and an ultrathin copper layer in this order, wherein D2-D1 is 0.30 to 3.83 μm, where D1 is the gravimetrically measured thickness of the carrier-attached copper foil excluding the carrier and the interlayer, and D2 is the maximum thickness of the layer remaining on a bismaleimide-triazine resin substrate in case of detaching the carrier after the carrier-attached copper foil is laminated to the resin substrate from the ultrathin copper layer side by being heat pressed under a pressure of 20 kgf/cm2 at 220° C. for 2 hours.

Abstract translation: 本文提供了具有所需的精细电路成形性的载体附着铜箔。 载体附着的铜箔依次包括载体，中间层和超薄铜层，D2-D1为0.30〜3.83μm，D1为载体附着铜箔的重量测定厚度，不包括载体， 中间层D2是在将载体附着铜箔从超薄铜层侧层压到树脂基板上之后通过热压下而分离载体的情况下，在双马来酰亚胺 - 三嗪树脂基板上残留的层的最大厚度 在220℃下压力为20kgf / cm 2小时。

公开(公告)号：US09516764B2

公开(公告)日：2016-12-06

申请号：US14778677

申请日：2014-03-25

Applicant: HITACHI CHEMICAL COMPANY, LTD.

Inventor： Nobuyuki Yoshida

IPC: H01B13/00 ,  H05K3/42 ,  C25D7/00 ,  C25D5/02 ,  C25D5/10 ,  C25D5/48 ,  C23C18/16 ,  H05K3/06 ,  C25D3/38 ,  C25D5/34 ,  C25D7/12 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K3/46 ,  C23C18/40 ,  H05K3/38

CPC classification number: H05K3/421 ,  C23C18/1653 ,  C23C18/405 ,  C25D3/38 ,  C25D5/02 ,  C25D5/10 ,  C25D5/34 ,  C25D5/48 ,  C25D7/00 ,  C25D7/123 ,  H05K1/0298 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/115 ,  H05K3/06 ,  H05K3/382 ,  H05K3/427 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2203/0353 ,  H05K2203/1423

Abstract: To provide a method for manufacturing a multilayer wiring substrate, in which an insulating layer and a metal foil provided thereon are integrally laminated on an inner layer material having a wiring formed thereon, in which a hole for via hole is formed in the metal foil and the insulating layer, and in which the hole for via hole is filled with an electrolytic filled plating layer after a base electroless plating layer is formed, the method being featured in that, after the base electroless plating layer is formed, first, an electrolysis filled plating layer is formed to the extent that the hole for via hole is not completely filled, and then, after the surface of the electrolytic filled plating layer is etched, the hole for via hole is completely filled by an electrolytic filled plating layer.

Abstract translation: 为了提供一种制造多层布线基板的方法，其中设置在其上的绝缘层和金属箔一体层压在其上形成有布线的内层材料上，其中在金属箔中形成有用于通孔的孔， 绝缘层，在形成基底化学镀层之后，通孔的孔填充有电解填充的镀层，其特征在于，在形成基底化学镀层之后，首先，填充电解液 形成电镀层的程度为通孔的孔未完全填充，然后在电解填充镀层的表面被蚀刻后，通孔的孔完全由电解填充镀层填充。

公开(公告)号：US20160353581A1

公开(公告)日：2016-12-01

申请号：US15039464

申请日：2014-11-27

Applicant: JX Nippon Mining & Metals Corporation

Inventor： Tomota Nagaura

IPC: H05K3/20 ,  B32B15/20 ,  C25D3/40 ,  H05K3/40 ,  H05K1/09 ,  H05K1/02 ,  H05K3/00 ,  H05K3/02 ,  B32B15/01 ,  C25D7/12

CPC classification number: H05K3/205 ,  B32B15/01 ,  B32B15/20 ,  B32B2307/306 ,  B32B2307/538 ,  B32B2457/08 ,  C25D1/04 ,  C25D3/16 ,  C25D3/38 ,  C25D3/40 ,  C25D3/58 ,  C25D5/04 ,  C25D5/14 ,  C25D5/48 ,  C25D7/0614 ,  C25D9/08 ,  H05K1/09 ,  H05K3/007 ,  H05K3/027 ,  H05K3/4038 ,  H05K2201/0338 ,  H05K2201/0355

Abstract: A carrier-attached copper foil having satisfactory circuit formability on the ultra-thin copper layer surface is provided. The carrier-attached copper foil has a carrier, an intermediate layer and an ultra-thin copper layer in this order. The ultra-thin copper layer surface has an absorbance of light at a wavelength of 400 nm is 85% or more.

Abstract translation: 提供了在超薄铜层表面上具有令人满意的电路成形性的载体附着铜箔。 载体附着铜箔依次具有载体，中间层和超薄铜层。 超薄铜层表面的波长为400nm的光的吸光度为85％以上。

公开(公告)号：US09480159B2

公开(公告)日：2016-10-25

申请号：US14520481

申请日：2014-10-22

Applicant: Koji Hachiya ,  Tomoyoshi Kobayashi ,  Koichi Nakabayashi

Inventor： Koji Hachiya ,  Tomoyoshi Kobayashi ,  Koichi Nakabayashi

IPC: H05K1/16 ,  H05K1/18

CPC classification number: H05K1/165 ,  H05K1/181 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2201/086 ,  H05K2201/09063

Abstract: A coil-integrated printed circuit board includes: a first outer layer which includes a first outer thick electric conductor made of a thick metallic foil and a first outer thin electric conductor made of a thin metallic foil having a thickness smaller than that of the first outer thick electric conductor, and which is exposed to an outside; and a first inner layer which includes an inner thick electric conductor made of a thick metallic foil, and which is not exposed to the outside. Coil patterns are respectively formed by the first outer thick electric conductor and the inner thick electric conductor. A first electronic component is surface-mounted on the first outer thin electric conductor provided on the outer layer.

Abstract translation: 线圈集成印刷电路板包括：第一外层，其包括由厚金属箔制成的第一外部厚电导体和由薄金属箔制成的第一外部薄导电体，该薄金属箔的厚度小于第一外部厚度 厚电导体，暴露于外部; 以及第一内层，其包括由厚金属箔制成且不暴露于外部的内部厚电导体。 线圈图案分别由第一外部厚电导体和内部厚电导体形成。 第一电子部件被表面安装在设置在外层上的第一外部薄导电导体上。