公开(公告)号：US20080087456A1

公开(公告)日：2008-04-17

申请号：US11871498

申请日：2007-10-12

Applicant: Franz Michael Schuette

Inventor： Franz Michael Schuette

IPC: H05K1/00 ,  H05K3/00

CPC classification number: H05K1/0207 ,  H05K1/0272 ,  H05K3/4641 ,  H05K2201/0281 ,  H05K2201/029 ,  H05K2201/0379 ,  H05K2201/064 ,  H05K2201/09681 ,  Y10T29/49124

Abstract: Circuit board assemblies and methods that employ integrated heatspreaders to cool the assemblies and serve as electrical ground planes for the assemblies. Such a circuit board assembly includes a substrate having at least one circuit device on at least a first surface thereof and an electrical ground plane. The circuit device has a first set of solder connections electrically connected to the electrical ground plane and a second set of solder connections electrically connected to power and signal traces on the first surface of the substrate. The assembly further includes a heatspreader embedded in the substrate and defining an electrical element of the electrical ground plane as a result of being electrically connected to the first set of solder connections. The heatspreader is configured as a plate-mesh-plate laminate that defines a cavity containing a fluid for transferring heat from the circuit device.

Abstract translation: 电路板组件和方法采用集成散热器来冷却组件并用作组件的电接地平面。 这种电路板组件包括在其至少第一表面上具有至少一个电路装置的基板和电接地平面。 电路装置具有电连接到电接地平面的第一组焊接连接和电连接到衬底的第一表面上的功率和信号迹线的第二组焊接连接。 组件还包括嵌入在基板中并且由于电连接到第一组焊接连接而限定电接地平面的电元件的散热器。 散热器被配置为板网板层压板，其限定包含用于从电路装置传递热量的流体的空腔。

公开(公告)号：US20080026557A1

公开(公告)日：2008-01-31

申请号：US11868912

申请日：2007-10-10

Applicant: Peter Salmon

Inventor： Peter Salmon

IPC: H01L21/441

CPC classification number: H05K3/363 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05573 ,  H01L2224/11332 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/81052 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3651 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4015 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/05599

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server or supercomputer embodiment is also described.

Abstract translation: 本说明书描述了用于制造电子系统模块的技术。 该模块包括具有窄至5微米或更小的迹线宽度的柔性多层互连电路。 与用于制造液晶显示器，LCD，面板的玻璃面板制造设备相似，优选地用于制造互连电路。 使用剥离层在玻璃面板上制造多层互连电路。 在互连电路上形成特殊的组装层，该电路包括在输入/输出（I / O）焊盘位置处形成有开口的厚电介质层。 使用刮刀将焊膏沉积在开口中以形成填充有焊料的孔。 IC芯片在I / O焊盘位置处设有金柱凸起，并且这些凸块插入孔中以形成倒装芯片连接。 IC芯片经过测试和返工。 相同的凹凸/连接可用于连接细间距电缆。 提供模块封装层用于密封和电磁屏蔽。 还描述了刀片服务器或超级计算机实施例。

公开(公告)号：US20080023841A1

公开(公告)日：2008-01-31

申请号：US11830505

申请日：2007-07-30

Applicant: Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

Inventor： Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

IPC: H01L23/48 ,  H01R12/04 ,  H05K3/02

CPC classification number: H05K3/305 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/0262 ,  H05K1/056 ,  H05K1/141 ,  H05K1/183 ,  H05K3/107 ,  H05K3/4614 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09972 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0278 ,  H05K2203/1189 ,  Y02P70/613 ,  Y10T29/49155

Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer. The first and second conductive parts form connecting areas in the insulating layer, thereby connecting the first and second circuit substrates electrically.

Abstract translation: 为了减少设置在芯基板上的电路基板与要安装在其上的电路之间的连接缺陷，从而提高作为多层器件安装基板的可靠性。 装置安装基板包括：由基板，形成在该基板上的绝缘层和形成在该绝缘层上的第一导电层（包括导电部分）构成的第一电路基板; 以及安装在第一电路基板上的第二电路基板，由基底，形成在基底的底部的第二导电层（包括导电部）和形成在基底的顶部的第三导电层 的基地。 这里，第一和第二电路基板通过压力接合，使得第一和第二导电部件层叠并嵌入到绝缘层中。 第一和第二导电部分形成绝缘层中的连接区域，从而电连接第一和第二电路基板。

公开(公告)号：US20070158103A1

公开(公告)日：2007-07-12

申请号：US11684147

申请日：2007-03-09

Applicant: Ryuichiro WADA ,  Tetsuya IKEDA

Inventor： Ryuichiro WADA ,  Tetsuya IKEDA

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H05K1/186 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/023 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/183 ,  H05K3/4614 ,  H05K3/4629 ,  H05K2201/0379 ,  H05K2201/091 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A chip-type electronic component built-in multilayer board includes a multilayer board including two or more layered dielectric layers and an inner conductor pattern, and a chip-type electronic component which is provided at the interface of the upper and lower dielectric layers and includes an external terminal electrode. The external terminal electrode is connected to an in-plane conductor provided at a interface via a first connection conductor extending along the chip-type electronic component in the lower direction from the interface of the upper and lower dielectric layers, and a second connection conductor extending along the chip-type electronic component in the upper direction from the interface of the upper and lower dielectric layers.

Abstract translation: 芯片型电子元件内置多层板包括：多层基板，包括两层或多层叠层电介质层和内导体图案;以及芯片型电子元件，其设置在上下电介质层的界面处，并包括 外部端子电极。 外部端子电极通过第一连接导体连接到设置在界面处的面内导体，所述第一连接导体沿着所述芯片型电子部件从所述上部和下部电介质层的界面向下方延伸;以及第二连接导体， 沿着芯片型电子部件从上下电介质层的界面向上方延伸。

公开(公告)号：US20060175702A1

公开(公告)日：2006-08-10

申请号：US11050450

申请日：2005-02-04

Applicant: Kazuo Ishibashi

Inventor： Kazuo Ishibashi

IPC: H01L23/48

CPC classification number: H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/0212 ,  H05K2201/0379 ,  H05K2201/10515 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A circuit assembly comprising a first circuit board and a second circuit board and an electrical connection between the first board and the second board, wherein the electrical connection comprises an outer coating of a electrically conductive first material and two inner cores of a second material, the first material having a lower melting point than the second material and the two cores being arranged to form a stack in which one of the cores is located between the other of the cores and one of the circuit boards.

Abstract translation: 一种电路组件，包括第一电路板和第二电路板以及第一板和第二板之间的电连接，其中电连接包括导电第一材料的外涂层和第二材料的两个内芯， 第一材料具有比第二材料低的熔点，并且两个芯布置成形成堆叠，其中一个芯位于另一个芯和一个电路板之间。

公开(公告)号：US20060102386A1

公开(公告)日：2006-05-18

申请号：US11252540

申请日：2005-10-19

Applicant: Shinji Morimoto ,  Kouji Nakashima ,  Toyokazu Yoshino ,  Katsuya Okamoto

Inventor： Shinji Morimoto ,  Kouji Nakashima ,  Toyokazu Yoshino ,  Katsuya Okamoto

IPC: H05K1/16

CPC classification number: H05K3/4635 ,  H05K1/0393 ,  H05K3/386 ,  H05K3/4046 ,  H05K3/4084 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/0221 ,  H05K2201/0379 ,  H05K2201/043 ,  H05K2201/096 ,  H05K2201/10234 ,  H05K2201/10416 ,  H05K2203/0278 ,  H05K2203/041 ,  H05K2203/082 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49165

Abstract: A multi-layered flexible print circuit board comprising an insulating layer, a circuit layer formed on the front and back surfaces of the insulating layer and a hole connecting between the circuit layers via the insulating layer, wherein there is provided an electrically-conductive member having a metal layer formed thereon at least on the surface thereof which is press-fitted into the hole to electrically conduct the circuit layer.

Abstract translation: 一种多层柔性印刷电路板，包括绝缘层，形成在绝缘层的前表面和后表面上的电路层和经由绝缘层连接在电路层之间的孔，其中设置有导电构件，其具有 至少在其表面上形成有金属层，该金属层压配合到孔中以导电电路层。

公开(公告)号：US06929971B2

公开(公告)日：2005-08-16

申请号：US10302254

申请日：2002-11-22

Applicant: Kensho Murata ,  Mutsumi Masumoto ,  Kenji Masumoto

Inventor： Kensho Murata ,  Mutsumi Masumoto ,  Kenji Masumoto

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L21/00

CPC classification number: H01L21/56 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/0508 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10234 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/13099

Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.

Abstract translation: 提高制造称为晶片级CSP的半导体器件的生产率和成本。 与本发明相关的半导体器件的制造方法包含形成布线（18）的每个工艺，其用于将每个电极焊盘（10a）和外部连接端子电连接到晶片（10）的顶部上， 形成半导体元件，连接通过其上的单独工艺预成型的导电球，接下来，用树脂（32）覆盖上述晶片，使得导电支撑柱（30）的上部暴露 。 在后面的处理中，焊球（34）被布置为导电支柱上部的外部连接端子，最后，通过沿着上述边界线对上述晶片进行切割而形成半导体元件 所述半导体元件。

公开(公告)号：US06927471B2

公开(公告)日：2005-08-09

申请号：US10237640

申请日：2002-09-06

Applicant: Peter C. Salmon

Inventor： Peter C. Salmon

IPC: H01L23/498 ,  H01L23/538 ,  H05K1/00 ,  H05K1/11 ,  H05K3/00 ,  H05K3/34 ,  H05K3/46 ,  H01L29/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L24/16 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/25 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4682 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/20751 ,  H01L2924/00

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer base layer is formed on a glass carrier with an intermediate release layer. Alternate layers of metal and dielectric are formed on the base layer, and patterned to create an array of multi-layer interconnection circuits on the glass panel. A thick layer of polymer is deposited on the interconnection circuit, and openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings to form wells filled with solder. After dicing the glass carrier to form separated interconnection circuits, IC chips are stud bumped and assembled using flip chip bonding, wherein the stud bumps on the components are inserted into corresponding wells on the interconnection circuits. The IC chips are tested and reworked to form tested circuit assemblies. Methods for connecting to testers and to other modules and electronic systems are described. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server embodiment is also described.

Abstract translation: 本说明书描述了用于制造电子系统模块的技术。 该模块包括轨迹宽度为5微米或更小的柔性多层互连电路。 用于制造液晶显示器，LCD，面板的玻璃面板制造设备用于制造互连电路。 在具有中间剥离层的玻璃载体上形成聚合物基层。 金属和电介质的交替层形成在基底层上，并被图案化以在玻璃面板上产生多层互连电路阵列。 在互连电路上沉积一层聚合物，并在输入/输出（I / O）焊盘位置形成开口。 将焊膏沉积在开口中以形成填充有焊料的孔。 在切割玻璃载体以形成分离的互连电路之后，使用倒装芯片接合对IC芯片进行螺柱凸起并组装，其中部件上的螺柱凸起插入到互连电路上的对应的孔中。 对IC芯片进行测试和返工以形成测试电路组件。 描述了连接到测试仪和其他模块和电子系统的方法。 提供模块封装层用于密封和电磁屏蔽。 还描述了刀片服务器实施例。

公开(公告)号：US20050138592A1

公开(公告)日：2005-06-23

申请号：US10740149

申请日：2003-12-17

Applicant: Thomas Morgan ,  James Jackson ,  Weston Roth

Inventor： Thomas Morgan ,  James Jackson ,  Weston Roth

IPC: G06F17/50 ,  H01L21/60 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/12 ,  H05K3/34 ,  H03K17/693

CPC classification number: G06F17/5068 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K1/112 ,  H05K3/0005 ,  H05K3/1225 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/0379 ,  H05K2201/09227 ,  H05K2201/094 ,  H05K2201/10734 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00

Abstract: Various methods and apparatuses are described in which a printed circuit board has trace lines. Input/output pads on the printed circuit board may have approximately the same width dimension as a trace line connected to those input/output pads. A first group of vias in the printed circuit board may be aligned into a planar line with a set corridor spacing between adjacent of groups of vias also aligned into a planar line with the same axis to allow a routing space for lines in multiple layers of the printed circuit board to occur in the routing space established by the set corridor spacing.

Abstract translation: 描述了各种方法和装置，其中印刷电路板具有迹线。 印刷电路板上的输入/输出焊盘可能具有与连接到那些输入/输出焊盘的迹线大致相同的宽度尺寸。 印刷电路板中的第一组通孔可以对齐成平面线，其中相邻的通孔组之间的集合的走廊间隔也被排列成具有相同轴线的平面线，以允许路线空间用于多层 印刷电路板发生在由设置的走廊间距建立的路线空间中。

公开(公告)号：US06903700B2

公开(公告)日：2005-06-07

申请号：US10133326

申请日：2002-04-29

Applicant: Kenichi Maruhashi ,  Masaharu Ito ,  Keiichi Ohata ,  Kazuhiro Ikuina ,  Takeya Hashiguchi

Inventor： Kenichi Maruhashi ,  Masaharu Ito ,  Keiichi Ohata ,  Kazuhiro Ikuina ,  Takeya Hashiguchi

IPC: H01P5/18 ,  H01Q13/10 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46 ,  H01P3/08

CPC classification number: H01P5/185 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01P5/187 ,  H01Q13/10 ,  H05K1/0237 ,  H05K1/0272 ,  H05K1/185 ,  H05K3/4614 ,  H05K3/4697 ,  H05K2201/0379 ,  H05K2201/0969 ,  H05K2201/10242 ,  H05K2201/10416 ,  H01L2224/0401

Abstract: A high frequency circuit substrate comprises a first high frequency circuit substrate including at least a first dielectric material layer, a first conductor layer, a second dielectric material layer and a second conductor layer, which are laminated in the named order, the first conductor layer having a first slot formed therein, and the second conductor layer forming a transmission line, the first dielectric material layer having a first opening exposing the first slot at its bottom. The high frequency circuit substrate also comprises a second high frequency circuit substrate including at least a third dielectric material layer, a third conductor layer, a fourth dielectric material layer and a fourth conductor layer, which are laminated in the named order, the third conductor layer having a second slot formed therein, and the fourth conductor layer forming a transmission line, the third dielectric material layer having a second opening exposing the second slot at its bottom. The first high frequency circuit substrate and the first high frequency circuit substrate are bonded to each other in such a manner that the first dielectric material layer and the third dielectric material layer are faced to each other and the first slot and the second slot are electromagnetically coupled, by inserting one side and the other side of a conductor plate having a through hole into the first opening and the second opening, respectively.

Abstract translation: 高频电路基板包括第一高频电路基板，该第一高频电路基板至少包括第一电介质材料层，第一导体层，第二介电材料层和第二导体层，其按顺序层叠，所述第一导体层具有 形成在其中的第一槽，并且所述第二导体层形成传输线，所述第一介电材料层具有在其底部暴露所述第一槽的第一开口。 高频电路基板还包括第二高频电路基板，其包括按照所述顺序层压的至少第三电介质材料层，第三导体层，第四电介质层和第四导体层，第三导体层 具有形成在其中的第二槽，并且所述第四导体层形成传输线，所述第三介电材料层具有在其底部暴露所述第二槽的第二开口。 第一高频电路衬底和第一高频电路衬底彼此接合，使得第一电介质材料层和第三电介质材料层相互面对，并且第一槽和第二槽电磁耦合 通过将具有通孔的导体板的一侧和另一侧分别插入第一开口和第二开口中。