公开(公告)号：US09099458B2

公开(公告)日：2015-08-04

申请号：US13539480

申请日：2012-07-01

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H05K1/11 ,  H05K1/09 ,  H01L23/498 ,  H05K3/46 ,  H05K1/02

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/0969 ,  Y10T29/49155 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern.

Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠的通孔的平板通孔平台。 镀层通孔着色包括蚀刻图案。

公开(公告)号：US20150034378A1

公开(公告)日：2015-02-05

申请号：US14446702

申请日：2014-07-30

Applicant: IBIDEN CO., LTD.

Inventor： Kazuki KAJIHARA ,  Yasuki Kimishima

IPC: H05K1/11 ,  H05K3/24 ,  H05K3/10

CPC classification number: H05K3/427 ,  H05K1/0366 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2203/1476 ,  H05K2203/1492

Abstract: A printed wiring board includes an insulative resin substrate having a penetrating hole, a first conductive layer formed on first surface of the substrate, a second conductive layer formed on second surface of the substrate on the opposite side, and a through-hole conductor formed in the penetrating hole and connecting the first and second conductive layers. The through-hole conductor includes a seed layer on inner wall of the penetrating hole, a first electrolytic plated layer on the seed layer such that the first plated layer is filling the space formed by the seed layer in the penetrating hole and forming recesses at the ends of the penetrating hole, respectively, and second electrolytic plated layers filling the recesses, respectively, and the second plated layers includes electrolytic plating having an average crystalline particle diameter greater than an average crystalline particle diameter of electrolytic plating forming the first plated layer.

Abstract translation: 印刷电路板包括具有贯通孔的绝缘树脂基板，形成在基板的第一表面上的第一导电层，在相对侧的基板的第二表面上形成的第二导电层，以及形成在 穿透孔并连接第一和第二导电层。 所述通孔导体在所述贯通孔的内壁上具有种子层，所述种子层上的第一电解电镀层，使得所述第一镀层在所述贯通孔中填充由所述籽晶层形成的空间， 并且第二镀层分别包括平均结晶粒径大于形成第一镀层的电解电镀的平均结晶粒径的电解电镀。

公开(公告)号：US20140353006A1

公开(公告)日：2014-12-04

申请号：US14153059

申请日：2014-01-12

Applicant: Zhen Ding Technology Co., Ltd.

Inventor： TAEKOO LEE

IPC: H05K3/46 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K1/186 ,  H05K1/188 ,  H05K3/007 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2203/0353

Abstract: A multilayer circuit board includes a wiring board, a first adhesive sheet, an electronic device, and a second adhesive sheet. The wiring board includes a first wiring layer and a second wiring layer. The first adhesive sheet is adjacent to the first wiring layer. The first adhesive sheet defines a second receiving hole. The second receiving hole and the first receiving hole cooperatively form a receiving cavity. The first adhesive sheet includes a supporting surface. The electronic device is received in the receiving cavity, and includes two electrodes. The second adhesive sheet is adjacent to the second wiring layer, and includes a bottom surface. The third wiring layer is formed on the supporting surface and contacts with the two electrodes. The fourth wiring layer is formed on the bottom surface.

Abstract translation: 多层电路板包括布线板，第一粘合片，电子装置和第二粘合片。 布线基板包括第一布线层和第二布线层。 第一粘合片与第一布线层相邻。 第一粘合片限定第二容纳孔。 第二接收孔和第一接收孔协作地形成接收腔。 第一粘合片包括支撑表面。 电子设备被容纳在接收腔中，并且包括两个电极。 第二粘合片与第二布线层相邻，并且包括底面。 第三布线层形成在支撑面上并与两个电极接触。 第四布线层形成在底面上。

公开(公告)号：US08866026B2

公开(公告)日：2014-10-21

申请号：US13569826

申请日：2012-08-08

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H05K1/11 ,  H05K1/09 ,  H05K3/46 ,  H01L23/498 ,  H05K1/02

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/0969 ,  Y10T29/49155 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface.

Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括厚度基本为3μm的板状通孔着落。 镀层通孔着色包括蚀刻图案和铜顶表面。

公开(公告)号：US08842440B2

公开(公告)日：2014-09-23

申请号：US13930617

申请日：2013-06-28

Applicant: Ibiden Co., Ltd.

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a printed circuit board includes forming an opening portion in a substrate, positioning chip capacitors in the opening portion of the substrate such that the chip capacitors are accommodated in the opening portion of the substrate, forming a buildup structure including an interlayer resin insulating layer and a conductive layer over a surface of the substrate and the chip capacitors accommodated in the opening portion of the substrate, and forming on a surface of the buildup structure bump structures positioned to mount an IC chip such that the chip capacitors in the opening portion of the substrate are positioned directly below the IC chip.

Abstract translation: 一种印刷电路板的制造方法，其特征在于，在基板上形成开口部，将所述基板的开口部中的芯片电容器定位，使得所述芯片电容器容纳在所述基板的开口部，形成包含层间树脂 绝缘层和在基板的表面上的导电层和容纳在基板的开口部分中的芯片电容器，并且在构成堆积结构的凸起结构的表面上形成，以便安装IC芯片，使得开口中的芯片电容器 基板的一部分直接位于IC芯片的正下方。

公开(公告)号：US08826530B2

公开(公告)日：2014-09-09

申请号：US12732635

申请日：2010-03-26

Applicant: Ayao Niki ,  Atsushi Ishida ,  Ryojiro Tominaga

Inventor： Ayao Niki ,  Atsushi Ishida ,  Ryojiro Tominaga

IPC: H01K3/10 ,  H05K3/46 ,  H05K3/00 ,  C25D7/12 ,  H05K3/42 ,  C25D5/02 ,  H05K3/38

CPC classification number: H05K3/0032 ,  C25D5/02 ,  C25D7/12 ,  C25D7/123 ,  H05K3/387 ,  H05K3/422 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09581 ,  H05K2201/09827 ,  H05K2203/095 ,  H05K2203/1572 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for manufacturing a substrate with a metal film includes preparing an insulative substrate having the first surface and the second surface on the opposite side of the first surface, forming in the insulative substrate a penetrating hole having the inner wall tapering from the first surface of the insulative substrate toward the second surface, forming a layer of a composition containing a polymerization initiator and a polymerizable compound on the inner wall of the penetrating hole, irradiating the layer of the composition with energy such that a polymer is formed on the inner wall of the penetrating hole, applying a plating catalyst on the polymer, and forming a plated-metal film on the inner wall of the penetrating hole.

Abstract translation: 一种用金属膜制造衬底的方法包括制备在第一表面的相对侧具有第一表面和第二表面的绝缘衬底，在绝缘衬底中形成具有从第一表面的第一表面逐渐变细的内壁的穿透孔 所述绝缘基板朝向所述第二表面，在所述穿透孔的内壁上形成含有聚合引发剂和可聚合化合物的组合物层，用能量照射所述组合物层，使得聚合物形成在所述聚合物的内壁上 穿孔，在聚合物上涂布电镀催化剂，在贯通孔的内壁上形成电镀金属膜。

公开(公告)号：US08822839B2

公开(公告)日：2014-09-02

申请号：US13307213

申请日：2011-11-30

Applicant: Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

Inventor： Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/3457 ,  H05K3/381 ,  H05K3/382 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0796 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a core substrate, lower interlayer resin insulating layers formed on the surfaces of the core substrate, respectively, through-hole conductors formed in penetrating holes penetrating through the core substrate and the lower interlayer resin insulating layers, conductor circuits formed on the lower interlayer resin insulating layers, respectively, upper interlayer resin insulating layers formed on the conductor circuits and the lower interlayer resin insulating layers, respectively and via hole conductors formed in the upper interlayer resin insulating layers and positioned on the through-hole conductors, respectively.

Abstract translation: 一种多层印刷电路板，包括芯基板，分别形成在芯基板的表面上的下层层间树脂绝缘层，形成在穿透芯基板的穿透孔中的通孔导体和下层间树脂绝缘层，导体 形成在下层树脂绝缘层上的电路分别形成在导体电路和下层间树脂绝缘层上的上层间树脂绝缘层和分别形成在上层间树脂绝缘层中并位于通孔上的通孔导体 导体。

公开(公告)号：US08754334B2

公开(公告)日：2014-06-17

申请号：US13433588

申请日：2012-03-29

Applicant: Yasushi Inagaki ,  Katsuyuki Sano

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H05K1/03

CPC classification number: H05K1/0237 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/0224 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09736 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An IC chip for a high frequency region, particularly a packaged substrate in which no malfunction or error occurs even if 3 GHz is exceeded. A conductive layer on a core substrate is formed at a thickness of 30 μm and a conductor circuit on an interlayer resin insulation layer is formed at a thickness of 15 μm. By thickening the conductive layer, the volume of the conductor can be increased and resistance can be reduced. Further, by using the conductive layer as a power source layer, the capacity of supply of power to an IC chip can be improved.

公开(公告)号：US20140144686A1

公开(公告)日：2014-05-29

申请号：US14093099

申请日：2013-11-29

Applicant: IBIDEN CO., LTD.

Inventor： Keisuke SHIMIZU

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/30

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09045 ,  H05K2201/09154 ,  H05K2201/09536 ,  H05K2203/167 ,  Y10T29/49139 ,  H01L2924/00

Abstract: A wiring board for a built-in electronic component includes a substrate having a cavity portion, an electronic component accommodated in the cavity portion of the substrate, a filling resin material filling a space formed between the electronic component and an inner wall of the substrate forming the cavity portion, an insulation layer formed on the substrate and the electronic component accommodated in the cavity portion of the substrate, and a via conductor formed in the insulation layer such that the via conductor is connected to a connection terminal of the electronic component. The substrate has projection portions formed on the inner wall of the substrate such that the projection portions project toward the electronic component accommodated in the cavity portion of the substrate.

Abstract translation: 一种用于内置电子元件的布线板，包括：具有空腔部分的基板;容纳在基板的空腔部分中的电子元件;填充树脂材料，填充电子元件与基板形成的内壁之间形成的空间 空腔部分，形成在基板上的绝缘层和容纳在基板的空腔部分中的电子部件以及形成在绝缘层中的通孔导体，使得通孔导体连接到电子部件的连接端子。 基板具有形成在基板的内壁上的突起部分，使得突出部分朝向容纳在基板的空腔部分中的电子部件突出。

公开(公告)号：US08717772B2

公开(公告)日：2014-05-06

申请号：US12566776

申请日：2009-09-25

Applicant: Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed circuit board includes a core substrate having an opening portion, an electronic component provided in the opening portion of the core substrate and including a dielectric body, a first electrode formed over the dielectric body, and a second electrode formed over the dielectric body such that the dielectric body is interposed between the first electrode and the second electrode, and a resin filling a gap between the core substrate and the electronic component in the opening portion of the core substrate. The resin filling the gap includes a filler.

Abstract translation: 印刷电路板包括具有开口部分的芯基板，设置在芯基板的开口部分中的电子部件，包括电介质体，形成在绝缘体上的第一电极和形成在电介质体上的第二电极， 介电体插入在第一电极和第二电极之间，以及树脂填充芯基板的开口部分中的芯基板和电子部件之间的间隙。 填充间隙的树脂包括填料。