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    WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME
    21.
    发明申请
    WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    接线板及其制造方法

    公开(公告)号：US20150075848A1

    公开(公告)日：2015-03-19

    申请号：US14552771

    申请日：2014-11-25

    Applicant: IBIDEN CO., LTD.

    Inventor： Nobuyuki NAGANUMA ,  Michimasa Takahashi ,  Masakazu Aoyama

    IPC: H05K1/11 ,  H05K3/46 ,  H05K1/18 ,  H05K3/00 ,  H05K1/09 ,  H05K1/02

    CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/116 ,  H05K1/18 ,  H05K3/0011 ,  H05K3/0094 ,  H05K3/4069 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09854 ,  Y10T156/1056

    Abstract: A wiring board includes multiple insulating layers including first, second, third, fourth and fifth insulation layers laminated in the order of the first, second, third, fourth and fifth insulation layers. The first insulation layer has a first conductor including plating, the second insulation layer has a second conductor including plating, the third insulation layer has a third conductor including conductive paste, the fourth insulation layer has a fourth conductor including plating, the fifth insulation layer has a fifth conductor including plating, and the first conductor, the second conductor, the third conductor, the fourth conductor and the fifth conductor are formed along the same axis and are electrically continuous with each other.

    Abstract translation: 布线板包括多个绝缘层，包括以第一，第二，第三，第四和第五绝缘层的顺序层叠的第一，第二，第三，第四和第五绝缘层。 所述第一绝缘层具有包括电镀的第一导体，所述第二绝缘层具有包括电镀的第二导体，所述第三绝缘层具有包括导电糊的第三导体，所述第四绝缘层具有包括电镀的第四导体，所述第五绝缘层具有 包括电镀的第五导体，并且第一导体，第二导​​体，第三导体，第四导体和第五导体沿着相同的轴线形成并且彼此电连接。

    CIRCUIT BOARD WITH INTEGRATED PASSIVE DEVICES
    22.
    发明申请
    CIRCUIT BOARD WITH INTEGRATED PASSIVE DEVICES 有权
    具有集成无源器件的电路板

    公开(公告)号：US20140116765A1

    公开(公告)日：2014-05-01

    申请号：US13664264

    申请日：2012-10-30

    Applicant: MD Altaf Hossain ,  Jin Zhao ,  John T. Vu

    Inventor： MD Altaf Hossain ,  Jin Zhao ,  John T. Vu

    IPC: H05K1/16 ,  H05K3/30

    CPC classification number: H05K1/183 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0326 ,  H05K1/113 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/32 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/09709 ,  H05K2201/0989 ,  H05K2201/10734 ,  Y10T29/4913

    Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例涉及具有诸如电感器，电容器，电阻器和相关技术和配置的集成无源器件的电路板。 在一个实施例中，一种装置包括具有与第一表面相对的第一表面和第二表面的电路板，以及与电路板成一体的无源器件，该无源器件具有被配置为与管芯的电力耦合的输入端子， 与输入端子电耦合的输出端子以及设置在电路板的第一表面和第二表面之间的电气路由特征，并且与输入端子和输出端子耦合以在输入端子和输出端子之间布置电力 ，其中所述输入端子包括被配置为接收包括所述管芯的封装组件的焊球连接的表面。 可以描述和/或要求保护其他实施例。

    WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME
    25.
    发明申请
    WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME 有权
    接线板及其制造方法

    公开(公告)号：US20110180908A1

    公开(公告)日：2011-07-28

    申请号：US12895126

    申请日：2010-09-30

    Applicant: Nobuyuki NAGANUMA ,  Michimasa Takahashi ,  Masakazu Aoyama

    Inventor： Nobuyuki NAGANUMA ,  Michimasa Takahashi ,  Masakazu Aoyama

    IPC: H01L29/41 ,  H01L21/36

    CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/116 ,  H05K1/18 ,  H05K3/0011 ,  H05K3/0094 ,  H05K3/4069 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09854 ,  Y10T156/1056

    Abstract: A wiring board includes a laminated body having first and second surfaces and including first, second and third insulation layers in the order of the first, second and third insulation layers from the first surface toward the second surface. The first insulation layer has a first hole which penetrates through the first insulation layer and includes a first conductor made of a plating in the first hole. The second insulation layer has a second hole which penetrates through the second insulation layer and includes a second conductor made of a conductive paste in the second hole. The third insulation layer has a third hole which penetrates through the third insulation layer and includes a third conductor made of a plating in the third hole. The first, second and third conductors are positioned along the same axis and are electrically continuous with each other.

    Abstract translation: 布线板包括具有第一表面和第二表面并且包括第一，第二和第三绝缘层从第一表面朝向第二表面的顺序的层叠体。 第一绝缘层具有穿过第一绝缘层的第一孔，并且包括在第一孔中由电镀制成的第一导体。 第二绝缘层具有穿过第二绝缘层的第二孔，并且包括在第二孔中由导电膏制成的第二导体。 第三绝缘层具有穿过第三绝缘层的第三孔，并且包括在第三孔中由电镀制成的第三导体。 第一，第二和第三导体沿着相同的轴定位并且彼此电连续。

    Circuit board structure
    27.
    发明授权
    Circuit board structure 有权
    电路板结构

    公开(公告)号：US07858885B2

    公开(公告)日：2010-12-28

    申请号：US11867647

    申请日：2007-10-04

    Applicant: Shih-Ping Hsu

    Inventor： Shih-Ping Hsu

    IPC: H01R12/04 ,  H05K1/11

    CPC classification number: H05K3/427 ,  H05K1/116 ,  H05K3/108 ,  H05K3/426 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2203/0353 ,  Y10T29/49123 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49163 ,  Y10T29/49165

    Abstract: The present invention provides a circuit board structure, the circuit board structure consisting of a carrier board having a first surface and an opposed second surface, the carrier board being formed with at least one through hole penetrating the first and second surfaces; a conductive pillar formed in the through hole by electroplating; and a first circuit layer and a second circuit layer respectively formed on the first and second surfaces of the carrier board, the first and second circuit layers being electrically connected to the two end portions of the conductive pillar, thereby reducing spacing between adjacent conductive pillars of the carrier board and achieving high density circuit layout.

    Abstract translation: 本发明提供一种电路板结构，所述电路板结构由具有第一表面和相对的第二表面的载体板组成，所述载体板形成有穿过所述第一表面和所述第二表面的至少一个通孔; 通过电镀形成在通孔中的导电柱; 以及分别形成在所述载板的所述第一和第二表面上的第一电路层和第二电路层，所述第一和第二电路层电连接到所述导电柱的两个端部，由此减小相邻导电柱之间的间隔 承载板实现高密度电路布局。

    WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
    28.
    发明申请
    WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    接线基板及其制造方法

    公开(公告)号：US20100101851A1

    公开(公告)日：2010-04-29

    申请号：US12606538

    申请日：2009-10-27

    Applicant: Shigetsugu Muramatsu ,  Yasuhiko Kusama

    Inventor： Shigetsugu Muramatsu ,  Yasuhiko Kusama

    IPC: H05K1/02 ,  H05K3/10

    CPC classification number: H05K1/116 ,  H05K3/108 ,  H05K3/421 ,  H05K3/4644 ,  H05K3/4647 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2203/0542 ,  H05K2203/0733 ,  Y10T29/49155 ,  Y10T29/49204

    Abstract: A wiring substrate, includes a first wiring layer, an insulating layer formed on the first wiring layer, a via conductor filled to penetrate the insulating layer in a thickness direction and connected to a connection portion of the first wiring layer, and a second wiring layer which is formed on the insulating layer and whose connection portion is connected to the via conductor, wherein, out of the first wiring layer and the second wiring layer, the connection portion of one wiring layer is formed as a land whose diameter is larger than a diameter of the via conductor, and the connection portion of other wiring layer is formed as a landless wiring portion whose diameter is equal to or smaller than a diameter of the via conductor.

    Abstract translation: 布线基板包括第一布线层，形成在第一布线层上的绝缘层，填充成在厚度方向上贯穿绝缘层并与第一布线层的连接部分连接的通孔导体，以及第二布线层 其形成在绝缘层上，其连接部分连接到通孔导体，其中，在第一布线层和第二布线层之外，一个布线层的连接部分形成为直径大于 通孔导体的直径和其他布线层的连接部分形成为直径等于或小于通路导体的直径的无地布线部分。

    Printed circuit board including landless via and method of manufacturing the same
    29.
    发明申请
    Printed circuit board including landless via and method of manufacturing the same 审中-公开
    包括无地面通孔及其制造方法的印刷电路板

    公开(公告)号：US20090294164A1

    公开(公告)日：2009-12-03

    申请号：US12219079

    申请日：2008-07-15

    Applicant: Han Kim ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Chang Gun Oh

    Inventor： Han Kim ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Chang Gun Oh

    IPC: H05K1/11 ,  H05K3/40

    CPC classification number: H05K1/116 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/025 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0394 ,  H05K2201/09545 ,  Y10T29/49165

    Abstract: Disclosed herein is a printed circuit board including a landless via and a method of manufacturing the printed circuit board. The printed circuit board includes a landless via having no upper land. The via includes a circuit pattern having a line width smaller than the minimum diameter of the via. The via does not have an upper land on an end surface thereof having the minimum diameter, and thus a circuit pattern connected to the via is finely formed, resulting in the high-density circuit pattern. Thus, a compact printed circuit board having a reduced number of layers is realized.

    Abstract translation: 本发明公开了一种印刷电路板，其包括无轨道通孔和制造印刷电路板的方法。 印刷电路板包括没有上部焊盘的无地通孔。 通孔包括具有小于通孔的最小直径的线宽的电路图案。 通孔在其端面上没有具有最小直径的上部焊盘，因此与通孔连接的电路图案被精细地形成，导致高密度电路图案。 因此，实现了层数减少的紧凑型印刷电路板。

    Method for Forming Resist Pattern, Method for Producing Circuit Board, and Circuit Board
    30.
    发明申请
    Method for Forming Resist Pattern, Method for Producing Circuit Board, and Circuit Board 失效
    形成抗蚀剂图案的方法，生产电路板和电路板的方法

    公开(公告)号：US20090236137A1

    公开(公告)日：2009-09-24

    申请号：US12227377

    申请日：2006-05-17

    Applicant: Yasuo Kaneda ,  Munetoshi Irisawa ,  Yuji Toyoda ,  Toyokazu Komuro ,  Katsuya Fukase ,  Toyoaki Sakai

    Inventor： Yasuo Kaneda ,  Munetoshi Irisawa ,  Yuji Toyoda ,  Toyokazu Komuro ,  Katsuya Fukase ,  Toyoaki Sakai

    IPC: H05K1/11 ,  G03F7/20

    CPC classification number: H05K3/426 ,  H05K1/116 ,  H05K3/002 ,  H05K3/108 ,  H05K2201/09545 ,  H05K2203/0191 ,  H05K2203/0574 ,  H05K2203/1184 ,  H05K2203/1394

    Abstract: There are provided a method for forming a resist pattern for preparing a circuit board having a landless or small-land-width through-hole(s) to realize a high-density circuit board, a method for producing a circuit board, and a circuit board. A method for forming a resist pattern, comprising the steps of forming a resin layer and a mask layer on a first surface of a substrate having a through-hole(s), and removing the resin layer on the through-hole(s) and on a periphery of the through-hole(s) on the first surface by supplying a resin layer removing solution from a second surface opposite to the first surface of the substrate, and a method for producing a circuit board using the method for forming a resist pattern, and a circuit board.

    Abstract translation: 提供了一种形成抗蚀剂图案的方法，该抗蚀剂图案用于制备具有无轨或小地平面宽度的通孔的电路板，以实现高密度电路板，生产电路板的方法和电路 板。 一种形成抗蚀剂图案的方法，包括以下步骤：在具有通孔的基板的第一表面上形成树脂层和掩模层，并且除去通孔上的树脂层和 通过从与基板的第一表面相对的第二表面提供树脂层去除溶液，在第一表面的通孔的周边上，以及使用该抗蚀剂形成方法制造电路板的方法 图案和电路板。

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