公开(公告)号：US20160373004A1

公开(公告)日：2016-12-22

申请号：US14901482

申请日：2014-05-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Nan ZHANG

IPC: H02M1/36

CPC classification number: H02M1/36 ,  H02M2001/0006

Abstract: A starting circuit (10) of a power management chip, comprising: a starting capacitor (C3) which is used for connecting a power supply via an external resistor (R2) to perform charging; a switch circuit (100) which is connected between the external resistor (R2) and the starting capacitor (C3); a voltage detection circuit (200) which is used for detecting a voltage on the starting capacitor (C3) and is connected to the switch circuit (100) so as to control the on/off switching of the switch circuit (100); and a voltage maintaining circuit (300) which is connected between the starting capacitor (C3) and an operating circuit of the power management chip and is used for acquiring a voltage that maintains the starting capacitor (C3) from the operating circuit of the power management chip, wherein when the voltage detection circuit (200) detects that the starting capacitor (C3) reaches the starting voltage of the power management chip, the broken circuit of the switch circuit (100) is controlled. Further provided is a power management chip including the above-mentioned starting circuit (10). Disconnecting an external power source from the starting capacitor after the operating circuit of the power management chip is started can reduce the electric energy consumption.

Abstract translation: 一种电源管理芯片的起动电路（10），包括：起动电容器（C3），用于经由外部电阻器（R2）连接电源以进行充电; 连接在外部电阻器（R2）和起动电容器（C3）之间的开关电路（100）; 用于检测起动电容器（C3）上的电压并连接到开关电路（100）的电压检测电路（200），以控制开关电路（100）的接通/断开开关; 以及连接在起动电容器（C3）和电源管理芯片的工作电路之间的电压保持电路（300），用于从电源管理的操作电路获取维持起动电容器（C3）的电压 芯片，其中当电压检测电路（200）检测到启动电容器（C3）达到电源管理芯片的启动电压时，开关电路（100）的断路被控制。 还提供了包括上述启动电路（10）的电源管理芯片。 在启动电源管理芯片的工作电路之后，断开外部电源与启动电容的连接可以减少电能消耗。

公开(公告)号：US09401422B2

公开(公告)日：2016-07-26

申请号：US14651706

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L21/265 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/66681 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: A trench-type DMOS device includes a substrate as a public drain region, an active region and a voltage-dividing ring formed on the substrate, and a first dielectric layer formed on the substrate. Multiple trenches are located on the first dielectric layer, and the trenches extend from the surface of the first dielectric layer into the interior of the substrate. The trenches comprise at least one first trench distributed in the active region and a second trench outside the active region. A gate oxide layer is formed in the trench and polycrystalline silicon is filled to form a gate. The active region further comprises a source electrode region and a P-type heavily doped region under the source electrode region. A second dielectric layer covers the first dielectric layer and the multiple trenches. A metal layer covers the second dielectric layer to form a first electrode region and a second electrode region.

Abstract translation: 沟槽型DMOS器件包括作为公共漏极区域的衬底，形成在衬底上的有源区和分压环，以及形成在衬底上的第一电介质层。 多个沟槽位于第一电介质层上，并且沟槽从第一电介质层的表面延伸到衬底的内部。 沟槽包括分布在有源区中的至少一个第一沟槽和在有源区之外的第二沟槽。 在沟槽中形成栅极氧化层，填充多晶硅以形成栅极。 有源区还包括在源电极区下面的源电极区和P型重掺杂区。 第二电介质层覆盖第一电介质层和多个沟槽。 金属层覆盖第二电介质层以形成第一电极区域和第二电极区域。

公开(公告)号：US20160181237A1

公开(公告)日：2016-06-23

申请号：US15055613

申请日：2016-02-28

Applicant: CSMC Technologies Fab1 Co., Ltd.

Inventor： Yonghai Hu ,  Meng Dai ,  Zhongyu Lin ,  Guangyang Wang

IPC: H01L27/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/40 ,  H01L21/3205 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L27/0255 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/32055 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/8232 ,  H01L27/0248 ,  H01L29/402 ,  H01L29/66121 ,  H01L29/87

Abstract: An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.

Abstract translation: 静电放电保护结构包括：第一导电类型的衬底，第二导电类型的阱区，衬底中的衬底接触区域和第一类型的导电性，阱区和第二类型的阱接触区域 在衬底接触区域和阱接触区域之间的导电性，衬底反掺杂区域和第二类型的导电性，衬底接触区域和阱接触区域之间的良好的反掺杂区域以及第一类型的导电性，通信 在衬底和阱区之间的横向结合处的区域，衬底反掺杂区域和连通区域之间的第一隔离区域，阱对掺杂区域和连通区域之间的第二隔离区域， 第一隔离区和衬底上的另一端，以及氧化物层上的场板结构。

公开(公告)号：US09356137B2

公开(公告)日：2016-05-31

申请号：US14130483

申请日：2013-05-07

Applicant: CSMC Technologies Fab1 Co., Ltd.

Inventor： Shu Zhang ,  Yanqiang He ,  TseHuang Lo ,  HsiaoChia Wu

IPC: H01L29/78 ,  H01L23/00 ,  H01L23/482

CPC classification number: H01L29/7816 ,  H01L23/4824 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/07 ,  H01L24/08 ,  H01L24/09 ,  H01L29/7835 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.

Abstract translation: 公开了功率MOS器件结构的各种实施例。 一方面，功率MOS器件结构包括多个LDMOS和多个接合焊盘。 LDMOS的基本单元并联并电耦合到焊盘，以耦合到LDMOS的每个基本单元的栅极端子，源极端子，漏极端子和衬底。 LDMOS的基本单元设置在焊盘下方。 接合焊盘包括厚度为3.5μm至4.5μm，宽度为1.5μm至2.5μm的单层金属。 本公开的功率MOS器件的焊盘下方的区域用于增加LDMOS的基本单元的数量，从而有效地降低导通电阻。

公开(公告)号：US09236306B2

公开(公告)日：2016-01-12

申请号：US14130476

申请日：2012-11-28

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Hsiaochia Wu ,  Shilin Fang ,  Tsehuang Lo ,  Zhengpei Chen ,  Shu Zhang ,  Yanqiang He

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823412 ,  H01L21/823456 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922

Abstract: A method for manufacturing a semiconductor device according to this specification solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The method is applicable to a BCD process and the like.

Abstract translation: 根据本说明书的制造半导体器件的方法解决了现有技术中的问题，即LDMOS漂移区域中的氧化物层的边缘上的硅容易暴露并导致LDMOS器件的击穿。 该方法包括：提供包括LDMOS区域和CMOS区域的半导体衬底; 在所述半导体衬底上形成牺牲氧化物层; 去除牺牲氧化物层; 在牺牲氧化处理后在半导体衬底上形成掩模层; 使用掩模层作为掩模形成LDMOS漂移区，以及在漂移区上方形成漂移区氧化物层; 并去除掩模层。 该方法适用于BCD处理等。

公开(公告)号：US20150162286A1

公开(公告)日：2015-06-11

申请号：US14411550

申请日：2012-10-22

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Zhongyu Lin ,  Meng Dai ,  Yonghai Hu

IPC: H01L23/60 ,  H01L27/02

CPC classification number: H01L23/60 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/7436 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device for electrostatic discharge protection includes a substrate, a first well and a second well formed in the substrate. The first and second wells are formed side by side, meeting at an interface, and have a first conductivity type and a second conductivity type, respectively. A first heavily doped region and a second heavily-doped region are formed in the first well. A third heavily doped region and a fourth heavily-doped region are formed in the second well. The first, second, third, and fourth heavily-doped regions have the first, second, second, and first conductivity types, respectively. Positions of the first and second heavily-doped regions are staggered along a direction parallel to the interface.

Abstract translation: 用于静电放电保护的半导体器件包括衬底，形成在衬底中的第一阱和第二阱。 第一和第二阱分别并列形成，在界面处相遇，分别具有第一导电型和第二导电型。 在第一阱中形成第一重掺杂区和第二重掺杂区。 在第二阱中形成第三重掺杂区和第四重掺杂区。 第一，第二，第三和第四重掺杂区域分别具有第一，第二，第二和第一导电类型。 第一和第二重掺杂区域的位置沿平行于界面的方向错开。

公开(公告)号：US20150137192A1

公开(公告)日：2015-05-21

申请号：US14407599

申请日：2013-06-10

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangtao Han

IPC: H01L29/808 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/808 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/402

Abstract: The present invention discloses a high voltage JFET. The high voltage JFET includes a second conductivity type drift region located on the first conductivity type epitaxial layer; a second conductivity type drain heavily doped region located in the second conductivity type drift region; a drain terminal oxygen region located on the second conductivity type drift region and at a side of the second conductivity type drain heavily doped region; a first conductivity type well region located at a side of the second conductivity type drift region; a second conductivity type source heavily doped region and a first conductivity type gate heavily doped region located on the first conductivity type well region, and a gate source terminal oxygen region; a second conductivity type channel layer located between the second conductivity type source heavily doped region and the second conductivity type drift region; a dielectric layer and a field electrode plate located on the second conductivity type channel layer. Wherein a drain electrode electrically is led out from the second conductivity type drain heavily doped region; a source electrode electrically is led out from a connection of the field electrode plate and the second conductivity type source heavily doped region; and a gate electrode electrically is led out from the first conductivity type gate heavily doped region. The transistor has a high breakdown voltage and easy to be integrated.

Abstract translation: 本发明公开了一种高电压JFET。 高电压JFET包括位于第一导电型外延层上的第二导电类型漂移区; 位于所述第二导电型漂移区域中的第二导电型漏极重掺杂区域; 位于所述第二导电型漂移区和所述第二导电型漏极重掺杂区的一侧的漏极端氧区; 位于第二导电型漂移区侧的第一导电型阱区; 第二导电型源极重掺杂区域和位于第一导电类型阱区域上的第一导电类型栅极重掺杂区域和栅极源极氧区域; 位于所述第二导电型源极重掺杂区域和所述第二导电型漂移区域之间的第二导电型沟道层; 位于第二导电型沟道层上的电介质层和场电极板。 其中漏极电极从第二导电类型漏极重掺杂区域引出; 源极电极从场电极板和第二导电类型源重掺杂区域的连接引出; 并且从第一导电型栅极重掺杂区域引出栅电极。 晶体管具有高击穿电压，易于集成。

公开(公告)号：US10301175B2

公开(公告)日：2019-05-28

申请号：US15327902

申请日：2015-08-20

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Errong Jing

IPC: B81B7/02 ,  B81C1/00 ,  G01J1/04 ,  G01J1/42 ,  G01J5/02

Abstract: A method for manufacturing a MEMS double-layer suspension microstructure comprises steps of: forming a first film body on a substrate, and a cantilever beam connected to the substrate and the first film body; forming a sacrificial layer on the first film body and the cantilever beam; patterning the sacrificial layer located on the first film body to manufacture a recessed portion used for forming a support structure, the bottom of the recessed portion being exposed of the first film body; depositing a dielectric layer on the sacrificial layer; patterning the dielectric layer to manufacture a second film body and the support structure, the support structure being connected to the first film body and the second film body; and removing the sacrificial layer to obtain the MEMS double-layer suspension microstructure.

公开(公告)号：US10101225B2

公开(公告)日：2018-10-16

申请号：US15119311

申请日：2015-05-06

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Dongbiao Qian

IPC: G01L1/24 ,  G01L1/04

Abstract: Provided is a pressure sensor that includes a detection film that is arranged on a silicon substrate, detects a pressure applied to a surface thereof, and generates a protrusion deformation in response to the pressure. The pressure sensor also includes an optical transmitter and an optical detector that are arranged on the silicon substrate on opposite sides of the detection film and are located at a plane parallel to a plane comprising the detection film. The pressure sensor also includes a pressure calculation module that is connected to the optical detector and is used for acquiring light intensity data and calculating a pressure value according to the light intensity data. Also provided is a method of manufacturing the pressure sensor.

公开(公告)号：US20180190815A1

公开(公告)日：2018-07-05

申请号：US15541661

申请日：2015-09-16

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangsheng ZHANG ,  Sen ZHANG ,  Peng BIAN ,  Xiaolong HU

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/49 ,  H01L29/36 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/7816 ,  H01L21/8238 ,  H01L21/823814 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7831 ,  H01L29/7835

Abstract: A high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10) comprises: a substrate (100); an N-type lateral double-diffused metal oxide semiconductor field effect transistor (200) formed on the substrate (100); and a P-type metal oxide semiconductor field effect transistor (300) formed at a drain of the N-type lateral double-diffused metal oxide semiconductor field effect transistor (200); wherein a gate of the P-type metal oxide semiconductor field effect transistor (300) serves as a gate of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10); a drain of the P-type metal oxide semiconductor field effect transistor (300) serves as a drain of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10); a source of the N-type lateral double-diffused metal oxide semiconductor field effect transistor (200) serves as a source of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10).