公开(公告)号：US10199224B2

公开(公告)日：2019-02-05

申请号：US15216951

申请日：2016-07-22

Applicant: Applied Materials, Inc.

Inventor： Zhigang Mao ,  Xiaoyi Chen ,  Amitabh Sabharwal ,  Ajay Kumar

IPC: H01L21/033 ,  G03F1/54 ,  G03F1/80 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/67 ,  G03F1/00 ,  C23F4/00 ,  G03F1/24 ,  H01L21/311

Abstract: Embodiments of the present invention provides methods to etching a mask layer, e.g., an absorber layer, disposed in a film stack for manufacturing a photomask in EUV applications and phase shift and binary photomask applications. In one embodiment, a method of etching an absorber layer disposed on a photomask includes transferring a film stack into an etching chamber, the film stack having a chromium containing layer partially exposed through a patterned photoresist layer, providing an etching gas mixture including Cl2, O2 and at least one hydrocarbon gas in to a processing chamber, wherein the Cl2 and O2 is supplied at a Cl2:O2 ratio greater than about 9, supplying a RF source power to form a plasma from the etching gas mixture, and etching the chromium containing layer through the patterned photoresist layer in the presence of the plasma.

公开(公告)号：US20180345418A1

公开(公告)日：2018-12-06

申请号：US15611015

申请日：2017-06-01

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei-Sheng Lei ,  Jungrae Park ,  Ajay Kumar ,  Brad Eaton

IPC: B23K26/40 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/308 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78 ,  B23K26/0622

CPC classification number: B23K26/0624 ,  B23K26/0661 ,  B23K26/18 ,  B23K26/364 ,  B23K26/402 ,  B23K2101/42 ,  B23K2103/50 ,  B23K2103/56 ,  H01L21/67092 ,  H01L21/67132 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/68381

Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a material layer over and between the plurality of singulated dies above the dicing tape. The method also includes expanding the dicing tape, wherein a plurality of particles is collected on the material layer during the expanding.

公开(公告)号：US09768014B2

公开(公告)日：2017-09-19

申请号：US14658102

申请日：2015-03-13

Applicant: Applied Materials, Inc.

Inventor： Jungrae Park ,  Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: B05C11/08 ,  B05C11/02 ,  B05C13/02 ,  B05C13/00 ,  H01L21/02 ,  B05B1/00 ,  B05B3/10 ,  H01L21/308 ,  H01L21/683 ,  H01L21/78 ,  H01L21/67

CPC classification number: H01L21/02282 ,  B05B1/00 ,  B05B3/1014 ,  B05B3/1035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/6715 ,  H01L21/6835 ,  H01L21/78 ,  H01L2221/68327

Abstract: Improved wafer coating processes, apparatuses, and systems are described. In one embodiment, an improved spin-coating process and system is used to form a mask for dicing a semiconductor wafer with a laser plasma dicing process. In one embodiment, a spin-coating apparatus for forming a film over a semiconductor wafer includes a rotatable stage configured to support the semiconductor wafer. The rotatable stage has a downward sloping region positioned beyond a perimeter of the semiconductor wafer. The apparatus includes a nozzle positioned above the rotatable stage and configured to dispense a liquid over the semiconductor wafer. The apparatus also includes a motor configured to rotate the rotatable stage.

公开(公告)号：US09412619B2

公开(公告)日：2016-08-09

申请号：US14458220

申请日：2014-08-12

Applicant: Applied Materials, Inc.

Inventor： Prabhat Kumar ,  Wei-Sheng Lei ,  Martin S. Wohlert ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/20 ,  H01L21/322 ,  H01L21/67 ,  H01L21/673 ,  H01L21/677

CPC classification number: H01L21/3221 ,  H01L21/3081 ,  H01L21/67115 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67393 ,  H01L21/67739 ,  H01L21/67748 ,  H01L21/78

Abstract: Embodiments of the invention include methods and apparatuses for outgassing a workpiece prior to a plasma processing operation. An embodiment of the invention may comprise transferring a workpiece having a mask to an outgassing station that has one or more heating elements. The workpiece may then be heated to an outgassing temperature that causes moisture from the mask layer to be outgassed. After outgassing the workpiece, the workpiece may be transferred to a plasma processing chamber. In an additional embodiment, one or more outgassing stations may be located within a process tool that has a factory interface, a load lock coupled to the factory interface, a transfer chamber coupled to the load lock, and a plasma processing chamber coupled to the transfer chamber. According to an embodiment, an outgassing station may be located within any of the components of the process tool.

Abstract translation: 本发明的实施例包括在等离子体处理操作之前使工件脱气的方法和装置。 本发明的实施例可以包括将具有掩模的工件传送到具有一个或多个加热元件的除气站。 然后可以将工件加热到使得来自掩模层的水分脱气的除气温度。 在对工件进行放气之后，可以将工件转移到等离子体处理室。 在另外的实施例中，一个或多个除气站可以位于处理工具内，该工具具有出厂界面，耦合到出厂界面的负载锁，耦合到负载锁的传送室以及耦合到传送的等离子体处理室 房间。 根据实施例，除气站可以位于处理工具的任何部件内。

公开(公告)号：US09269604B2

公开(公告)日：2016-02-23

申请号：US14542422

申请日：2014-11-14

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/301 ,  H01L21/683 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67 ,  B32B37/00 ,  B32B37/22 ,  B32B3/26

CPC classification number: H01L21/6836 ,  B32B3/266 ,  B32B37/0076 ,  B32B37/22 ,  B32B2307/202 ,  B32B2457/14 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/67092 ,  H01L21/67132 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of reducing edge warping in a supported semiconductor wafer involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier comprising a tape frame mounted above the carrier tape. The method also involves adhering an adhesive tape to a front side of the semiconductor wafer and to at least a portion of the substrate carrier. The adhesive tape includes an opening exposing an inner region of the front side of the semiconductor wafer.

Abstract translation: 对具有多个集成电路的各晶片的切割半导体晶片的方法和装置进行说明。 在一个示例中，减少支撑的半导体晶片中的边缘翘曲的方法包括将半导体晶片的背面粘附到包括安装在载带上方的带框架的基板载体的载带的内部。 该方法还包括将粘合带粘附到半导体晶片的正面以及衬底载体的至少一部分。 胶带包括露出半导体晶片正面的内部区域的开口。

公开(公告)号：US09250514B2

公开(公告)日：2016-02-02

申请号：US14199575

申请日：2014-03-06

Applicant: Applied Materials, Inc.

Inventor： Banqiu Wu ,  Ajay Kumar

IPC: C03C15/00 ,  G03F1/80 ,  G03F1/22

CPC classification number: G03F1/80 ,  G03F1/22

Abstract: An apparatus and methods utilized a DC or AC power to supply through a conductive substrate support pedestal to a conductive photomask substrate during a photomask substrate manufacturing process for EUV or other advanced lithography applications are provided. In one embodiment, an apparatus for processing a photomask includes a substrate support pedestal configured to receive a conductive photomask, wherein the conductive photomask is fabricated from a dielectric material substrate with a conductive coating, and at least a conductive path formed in the substrate support pedestal in contact with the photomask substrate configured to be conductive.

Abstract translation: 提供了一种在用于EUV或其它先进光刻应用的光掩模衬底制造过程中利用DC或AC电力通过导电衬底支撑基座提供给导电光掩模衬底的装置和方法。 在一个实施例中，一种用于处理光掩模的设备包括被配置为接收导电光掩模的基板支撑基座，其中导电光掩模由具有导电涂层的介电材料基板制成，并且至少形成在基板支撑基座中的导电路径 与配置为导电的光掩模基板接触。

公开(公告)号：US09236305B2

公开(公告)日：2016-01-12

申请号：US14158529

申请日：2014-01-17

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Saravjeet Singh ,  Jivko Dinev ,  Aparna Iyer ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/027 ,  H01L21/311 ,  H01J37/32 ,  H01L21/683 ,  B23K26/36 ,  B23K26/40

CPC classification number: H01L21/78 ,  B23K26/364 ,  B23K26/40 ,  B23K26/402 ,  B23K2103/172 ,  B23K2103/50 ,  H01J37/32009 ,  H01L21/0271 ,  H01L21/3065 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381

Abstract: Laser and plasma etch wafer dicing where a mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a film frame by an adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The laser scribing exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask while the film frame is maintained at an acceptably low temperature with a chamber shield ring configured to sit beyond the wafer edge and cover the frame. The shield ring may be raised and lowered, for example, on lifter pins to facilitate transfer of the wafer on frame.

Abstract translation: 激光和等离子体蚀刻晶片切割，其中形成掩模以覆盖形成在晶片上的IC，以及提供与IC的界面的任何凸块。 半导体晶片通过粘合膜耦合到胶片框架。 通过激光划线将掩模图案化以提供具有间隙的图案化掩模。 激光划线使半导体晶片的区域露出在形成有IC的薄膜层的下方。 半导体晶片通过图案化掩模中的间隙进行等离子体蚀刻，同时膜框架被保持在可接受的低温下，腔室屏蔽环被配置为超过晶片边缘并覆盖框架。 屏蔽环可以升高和降低，例如在升降器销上，以促进晶片在框架上的传送。

公开(公告)号：US09177864B2

公开(公告)日：2015-11-03

申请号：US14478354

申请日：2014-09-05

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Aparna Iyer ,  Todd Egan ,  Madhava Rao Yalamanchili ,  Ajay Kumar

IPC: H01L21/00 ,  H01L21/82 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/82 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/31127 ,  H01L21/78

Abstract: Methods of using a hybrid mask composed of a first water soluble film layer and a second water-soluble layer for wafer dicing using laser scribing and plasma etch described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a hybrid mask above the semiconductor wafer. The hybrid mask is composed of a first water-soluble layer disposed on the integrated circuits, and a second water-soluble layer disposed on the first water-soluble layer. The method also involves patterning the hybrid mask with a laser scribing process to provide a patterned hybrid mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also involves etching the semiconductor wafer through the gaps in the patterned hybrid mask to singulate the integrated circuits.

Abstract translation: 使用由第一水溶性薄膜层和第二水溶性层组成的晶片切割的激光划线和等离子体蚀刻的方法。 在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成混合掩模。 混合掩模由设置在集成电路上的第一水溶性层和设置在第一水溶性层上的第二水溶性层组成。 该方法还包括用激光划线工艺图案化混合掩模，以提供具有间隙的图案化混合掩模，暴露集成电路之间的半导体晶片的区域。 该方法还包括通过图案化混合掩模中的间隙蚀刻半导体晶片以对集成电路进行分离。

公开(公告)号：US09130030B1

公开(公告)日：2015-09-08

申请号：US14200918

申请日：2014-03-07

Applicant: Applied Materials, Inc.

Inventor： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/46 ,  H01L21/78 ,  B23K26/36 ,  B23K10/00

CPC classification number: H01L21/78 ,  B23K26/0823 ,  B23K26/0869 ,  B23K26/20 ,  B23K2101/001 ,  B23K2101/36 ,  B23K2103/166 ,  B23K2103/56

Abstract: Baking methods and tools for improved wafer coating are described. In one embodiment, a method of dicing a semiconductor wafer including integrated circuits involves coating a surface of the semiconductor wafer to form a mask covering the integrated circuits. The method involves baking the mask with radiation from one or more light sources. The method involves patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the substrate between the ICs. The method may also involves singulating the ICs, such as with a plasma etching operation.

Abstract translation: 描述了用于改进晶片涂层的烘烤方法和工具。 在一个实施例中，包括集成电路的半导体晶片的切割方法包括涂覆半导体晶片的表面以形成覆盖集成电路的掩模。 该方法包括用来自一个或多个光源的辐射来烘烤该掩模。 该方法包括用激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模，暴露在IC之间的衬底区域。 该方法还可以包括例如用等离子体蚀刻操作来分离IC。

公开(公告)号：US08980727B1

公开(公告)日：2015-03-17

申请号：US14272111

申请日：2014-05-07

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/00 ,  H01L21/3065 ,  C03C15/00 ,  H01L21/768

CPC classification number: H01L21/3065 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50 ,  C03C23/0025 ,  C03C23/006 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/00

Abstract: Approaches for patterning semiconductor or other wafers and dies are described. For example, a method of patterning features within a substrate involves forming a mask layer above a surface of a semiconductor or glass substrate. The method also involves laser ablating the mask layer to provide a pattern of openings through the mask layer. The method also involves plasma etching portions of the semiconductor or glass substrate through the pattern of openings to provide a plurality of trenches in the semiconductor or glass substrate. The plurality of trenches has a pattern corresponding to the pattern of openings and comprising a pattern of through-substrate-via openings or redistribution layer (RDL) openings. The method also involves, subsequent to the plasma etching, removing the mask layer.

Abstract translation: 描述用于图案化半导体或其它晶片和裸片的方法。 例如，在衬底内构图特征的方法包括在半导体或玻璃衬底的表面上形成掩模层。 该方法还涉及激光烧蚀掩模层以提供通过掩模层的开口图案。 该方法还包括通过开口图案等离子体蚀刻半导体或玻璃基板的部分，以在半导体或玻璃基板中提供多个沟槽。 多个沟槽具有与开口图案相对应的图案，并且包括贯穿基板通孔开口或再分布层（RDL）开口的图案。 该方法还包括在等离子体蚀刻之后，去除掩模层。