公开(公告)号：US20170358490A1

公开(公告)日：2017-12-14

申请号：US15332737

申请日：2016-10-24

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Sean KANG ,  Keith Tatseun WONG ,  He REN ,  Mehul B. NAIK ,  Ellie Y. YIEH ,  Srinivas D. NEMANI

IPC: H01L21/768

CPC classification number: H01L21/76882 ,  H01L21/76883 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53257

Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.

公开(公告)号：US20170098575A1

公开(公告)日：2017-04-06

申请号：US15285011

申请日：2016-10-04

Applicant: APPLIED MATERIALS, INC.

Inventor： Sree Rangasai V. KESAPRAGADA ,  Kevin MORAES ,  Srinivas GUGGILLA ,  He REN ,  Mehul NAIK ,  David THOMPSON ,  Weifeng YE ,  Yana CHENG ,  Yong CAO ,  Xianmin TANG ,  Paul F. MA ,  Deenesh PADHI

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76832 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US20160379819A1

公开(公告)日：2016-12-29

申请号：US14750778

申请日：2015-06-25

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Mehul B. NAIK ,  Deenesh PADHI ,  Priyanka DASH ,  Bhaskar KUMAR ,  Alexandros T. DEMOS

IPC: H01L21/02

CPC classification number: H01L21/02126 ,  C23C16/045 ,  C23C16/36 ,  C23C16/482 ,  C23C16/56 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02359 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831

Abstract: A method for sealing porous low-k dielectric films is provided. The method comprises exposing a substrate to UV radiation and a first reactive gas, wherein the substrate has an open feature defined therein, the open feature defined by a porous low-k dielectric layer and a conductive material, wherein the porous low-k dielectric layer is a silicon and carbon containing material and selectively forming a pore sealing layer in the open feature on exposed surfaces of the porous low-k dielectric layer using UV assisted photochemical vapor deposition.

Abstract translation: 提供了一种用于密封多孔低k电介质膜的方法。 该方法包括将衬底暴露于UV辐射和第一反应气体，其中衬底具有限定在其中的开放特征，由多孔低k电介质层和导电材料限定的开放特征，其中多孔低k电介质层 是含硅和碳的材料，并使用UV辅助光化学气相沉积在多孔低k电介质层的暴露表面上的开放特征中选择性地形成孔密封层。

公开(公告)号：US20150279726A1

公开(公告)日：2015-10-01

申请号：US14657827

申请日：2015-03-13

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Mehul B. NAIK

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32136 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76889

Abstract: Embodiments described herein relate to methods for forming an air gap interconnect. A metal spacer layer is conformally deposited on a substrate having mandrel structures formed thereon. The metal spacer layer is etched to form spacer features and the mandrel structures are removed from the substrate. Various other dielectric deposition, patterning and etching steps may be performed to desirably pattern materials present on the substrate. Ultimately, a trench is formed between adjacent spacer features and a capping layer is deposited over the trench to form an air gap between the adjacent spacer features. For packaging purposes, an interconnect via may be configured to contact at least one of the spacer features adjacent the air gap.

Abstract translation: 本文所述的实施例涉及形成气隙互连的方法。 金属间隔层共形沉积在其上形成有心轴结构的基底上。 蚀刻金属间隔层以形成间隔件特征，并且将芯棒结构从基底上移除。 可以进行各种其它介电沉积，图案化和蚀刻步骤以期望地存在于基板上的材料。 最终，在相邻间隔物特征之间形成沟槽，并且在沟槽上沉积覆盖层以在相邻间隔物特征之间形成气隙。 为了包装目的，互连通孔可以被配置为接触邻近气隙的间隔件特征中的至少一个。

公开(公告)号：US20150214101A1

公开(公告)日：2015-07-30

申请号：US14540577

申请日：2014-11-13

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Chia-Ling KAO ,  Sean KANG ,  Jeremiah T P PENDER ,  Srinivas D. NEMANI ,  Mehul B. NAIK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/308 ,  H01J37/32357 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813

Abstract: Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.

Abstract translation: 提供了用于消除双镶嵌结构中的导电层的早期暴露并用于蚀刻双镶嵌结构中的介电阻挡层的方法。 在一个实施例中，用于蚀刻设置在衬底上的电介质阻挡层的方法包括使用设置在介电体绝缘层上的硬掩模层作为蚀刻掩模来图案化设置在电介质阻挡层上的介电体绝缘层的衬底， 在去除绝缘体绝缘层未覆盖的绝缘体绝缘层之后，从基板去除硬掩模层，随后蚀刻由绝缘体绝缘层暴露的电介质阻挡层的部分介电阻挡层。

公开(公告)号：US20150170956A1

公开(公告)日：2015-06-18

申请号：US14523523

申请日：2014-10-24

Applicant: Applied Materials, Inc.

Inventor： Mehul B. NAIK ,  He REN ,  Zhenjiang CUI

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/7682 ,  C23C16/303 ,  C23C16/36 ,  H01J37/32082 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76819 ,  H01L21/76832 ,  H01L21/76834

Abstract: A method for forming an air gap structure in an integrated layer stack includes dry etching a mold layer disposed on the stack in a processing system under vacuum. The mold layer is disposed between one or more interconnects, and the process of dry etching of the mold layer exposes at least a portion of the interconnects. The method also includes depositing a liner layer over the exposed portion of the interconnects. In another embodiment, a method for forming an air gap structure in an integrated layer stack includes dry etching an oxide mold layer disposed on the stack in an a first processing chamber in a processing system under vacuum. The method also includes depositing a low-k material liner layer over the interconnects, wherein the liner has a thickness of less than about 2 nanometers. The methods disclosed herein are performed in a processing system without breaking vacuum.

Abstract translation: 在一体层叠体中形成气隙结构的方法包括在真空下在处理系统中干燥蚀刻设置在堆叠上的模具层。 模具层设置在一个或多个互连之间，并且模具层的干蚀刻的过程暴露至少一部分互连。 该方法还包括在互连的暴露部分上沉积衬垫层。 在另一实施例中，在一体层叠体中形成气隙结构的方法包括在真空下在处理系统中的第一处理室中干燥蚀刻设置在堆叠上的氧化物模层。 所述方法还包括在所述互连件上沉积低k材料衬垫层，其中所述衬垫具有小于约2纳米的厚度。 本文公开的方法在不破坏真空的处理系统中进行。