APPARATUS, SYSTEMS, AND METHODS FOR TEMPERATURE CONTROL OF SUBSTRATES USING EMBEDDED FIBER OPTICS AND EPOXY OPTICAL DIFFUSERS
    31.
    发明申请
    APPARATUS, SYSTEMS, AND METHODS FOR TEMPERATURE CONTROL OF SUBSTRATES USING EMBEDDED FIBER OPTICS AND EPOXY OPTICAL DIFFUSERS 审中-公开
    使用嵌入式光纤和环氧光学扩散器的基板温度控制的装置,系统和方法

    公开(公告)号:US20160007412A1

    公开(公告)日:2016-01-07

    申请号:US14738448

    申请日:2015-06-12

    Abstract: Substrate temperature control apparatus and electronic device manufacturing systems provide pixelated light-based heating to a substrate in a process chamber. A substrate holder in the process chamber may include a baseplate. The baseplate has a top surface that may have a plurality of cavities and a plurality of grooves connected to the cavities. Optical fibers may be received in the grooves such that each cavity has a respective optical fiber terminating therein to transfer light thereto. Some or all of the cavities may have an epoxy optical diffuser disposed therein to diffuse light provided by the optical fiber. A ceramic plate upon which a substrate may be placed may be bonded to the baseplate. A thermal spreader plate may optionally be provided between the baseplate and the ceramic plate. Methods of controlling temperature across a substrate holder in an electronic device manufacturing system are also provided, as are other aspects.

    Abstract translation: 基板温度控制装置和电子装置制造系统向处理室中的基板提供像素化的基于光的加热。 处理室中的衬底保持器可以包括底板。 底板具有可以具有多个空腔的顶表面和连接到空腔的多个凹槽。 光纤可以被容纳在槽中,使得每个空腔具有终止于其中的相应光纤以将光传送到其上。 一些或所有空腔可以具有设置在其中的环氧光学漫射器以漫射由光纤提供的光。 可以将衬底放置在其上的陶瓷板可以结合到基板。 可以可选地在基板和陶瓷板之间设置散热板。 还提供了在电子设备制造系统中控制衬底保持器温度的方法,以及其他方面。

    METHOD AND SYSTEM FOR WAFER LEVEL SINGULATION
    34.
    发明申请
    METHOD AND SYSTEM FOR WAFER LEVEL SINGULATION 审中-公开
    用于水平层叠的方法和系统

    公开(公告)号:US20140196850A1

    公开(公告)日:2014-07-17

    申请号:US14075603

    申请日:2013-11-08

    Abstract: A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.

    Abstract translation: 单片化多个半导体管芯的方法包括提供载体衬底并将半导体衬底接合到载体衬底。 半导体衬底包括多个器件。 该方法还包括在半导体衬底上形成掩模层,将掩模层的预定部分暴露于光,以及处理掩模层的预定部分以在半导体衬底上形成预定的掩模图案。 所述方法还包括形成所述多个半导体管芯,所述多个半导体管芯中的每一个与所述预定掩模图案相关联并且包括所述多个器件中的一个或多个并且将所述多个半导体管芯与所述载体衬底分离。

    RECONFIGURABLE MAINFRAME WITH REPLACEABLE INTERFACE PLATE

    公开(公告)号:US20250125170A1

    公开(公告)日:2025-04-17

    申请号:US18991285

    申请日:2024-12-20

    Inventor: Michael R. Rice

    Abstract: A mainframe of a device fabrication system comprises a base and a plurality of facets on the base, wherein a first facet of the plurality of facets comprises a first frame comprising a first column on a first side of the first facet, a second column on a second side of the first facet, and a beam connecting the first column to the second column. The mainframe further comprises a lid over the plurality of facets, wherein the base, the lid and the plurality of facets together define an interior volume. A first replaceable interface plate is sealed to the first frame of the first facet. The first column of the first facet comprises a first channel that fluidly couples a first vacuum region associated with the first replaceable interface plate to a vacuum port.

    Substrate processing systems, apparatus, and methods with substrate carrier and purge chamber environmental controls

    公开(公告)号:US11782404B2

    公开(公告)日:2023-10-10

    申请号:US17219692

    申请日:2021-03-31

    CPC classification number: G05B15/02 H01L21/67775

    Abstract: A system comprises a factory interface (FI) comprising an FI chamber and a carrier purge chamber, the FI configured to receive a substrate carrier that becomes coupled to the FI such that the carrier purge chamber is positioned between the FI chamber and the substrate carrier, the substrate carrier comprising a carrier door. The system further comprises an environmental control system coupled to at least one of the FI chamber or the carrier purge chamber and configured to couple to the substrate carrier, the environmental control system operable to separately control environmental conditions within at least one of: the carrier purge chamber and the substrate carrier; the carrier purge chamber and the FI chamber; or the FI chamber and the substrate carrier, while the carrier door of the substrate carrier is closed.

    Mainframe of substrate processing system

    公开(公告)号:USD992611S1

    公开(公告)日:2023-07-18

    申请号:US29859229

    申请日:2022-11-08

    Abstract: FIG. 1 is a top perspective view of a mainframe for substrate processing system of the present design.
    FIG. 2 is a side view thereof.
    FIG. 3 is a side view thereof.
    FIG. 4 is a front view thereof.
    FIG. 5 is a rear view thereof.
    FIG. 6 is a top view thereof.
    FIG. 7 is a bottom view thereof; and,
    FIG. 8 is a top perspective view thereof, showing unclaimed components attached thereto.
    The broken lines shown in the figures are directed to unclaimed portions of the mainframe and/or unclaimed components attached to the mainframe that are for illustrative purposes only and form no part of the claimed design.

    Mainframe of substrate processing system

    公开(公告)号:USD991994S1

    公开(公告)日:2023-07-11

    申请号:US29859227

    申请日:2022-11-08

    Abstract: FIG. 1 is a top perspective view of a mainframe for substrate processing system of the present design.
    FIG. 2 is a side view thereof.
    FIG. 3 is a side view thereof.
    FIG. 4 is a front view thereof.
    FIG. 5 is a rear view thereof.
    FIG. 6 is a top view thereof.
    FIG. 7 is a bottom view thereof; and,
    FIG. 8 is a top perspective view thereof, showing unclaimed components attached thereto.
    The broken lines shown in the figures are directed to unclaimed portions of the mainframe and/or unclaimed components attached to the mainframe that are for illustrative purposes only and form no part of the claimed design.

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