公开(公告)号：US20230086917A1

公开(公告)日：2023-03-23

申请号：US18052542

申请日：2022-11-03

Applicant: Applied Materials, Inc.

Inventor： Yi Zhou ,  Seul Ki Ahn ,  Seung-Young Son ,  Li-Te Chang ,  Sunil Srinivasan ,  Rajinder Dhindsa

IPC: H01J37/32 ,  H01L21/67 ,  H01L21/683 ,  C23C16/44 ,  H01L21/3065 ,  B08B7/00

Abstract: A method for removing etchant byproduct from an etch reactor and discharging a substrate from an electrostatic chuck of the etch reactor is provided. One or more layers on a substrate electrostatically secured to an electrostatic chuck within a chamber of the etch reactor is etched using a first plasma, causing an etchant byproduct to be generated. A portion of the one or more layers are covered by a photoresist. After the etching is complete, a second plasma is provided into the chamber for a time period sufficient to trim the photoresist and remove a portion of the etchant byproduct. A second time period sufficient to electrostatically discharge the substrate using the second plasma is determined. Responsive to deactivating one or more chucking electrodes of the electrostatic chuck, the second plasma is provided into the chamber for the second time period and the substrate is removed from the chamber.

公开(公告)号：US11515166B2

公开(公告)日：2022-11-29

申请号：US17371176

申请日：2021-07-09

Applicant: Applied Materials, Inc.

Inventor： Alvaro Garcia De Gorordo ,  Zhonghua Yao ,  Sunil Srinivasan ,  Sang Wook Park

IPC: H01L21/306 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/311

Abstract: A method for etching silicon at cryogenic temperatures is provided. The method includes forming an inert layer from condensation of a noble gas at cryogenic temperatures on exposed surfaces such as the sidewalls of a feature to passivate the sidewalls prior to the etching process. The method further includes flowing a fluorine-containing precursor gas into the chamber to form a fluorine-containing layer on the inert layer. The method further includes exposing the fluorine-containing layer and the inert layer to an energy source to form a passivation layer on the exposed portions of the substrate and exposing the substrate to ions to etch the substrate.

公开(公告)号：US11284500B2

公开(公告)日：2022-03-22

申请号：US16933311

申请日：2020-07-20

Applicant: Applied Materials, Inc.

Inventor： Leonid Dorf ,  Olivier Luere ,  Rajinder Dhindsa ,  James Rogers ,  Sunil Srinivasan ,  Anurag Kumar Mishra

IPC: H01J37/32 ,  H05H1/46 ,  H01J37/34 ,  H01J37/08 ,  C23C14/34 ,  C23C14/54

Abstract: Embodiments of this disclosure describe an electrode biasing scheme that enables maintaining a nearly constant sheath voltage and thus creating a mono-energetic IEDF at the surface of the substrate that consequently enables a precise control over the shape of IEDF and the profile of the features formed in the surface of the substrate.

公开(公告)号：US10553404B2

公开(公告)日：2020-02-04

申请号：US15421726

申请日：2017-02-01

Applicant: Applied Materials, Inc.

Inventor： Olivier Luere ,  Leonid Dorf ,  Sunil Srinivasan ,  Rajinder Dhindsa ,  James Rogers ,  Denis M. Koosau

IPC: H01J37/32 ,  H01L21/687 ,  H01L21/683

Abstract: Embodiments described herein generally related to a substrate processing apparatus. In one embodiment, a process kit for a substrate processing chamber disclosed herein. The process kit includes a ring having a first ring component and a second ring component, an adjustable tuning ring, and an actuating mechanism. The first ring component is interfaced with the second ring component such that the second ring component is movable relative to the first ring component forming a gap therebetween. The adjustable tuning ring is positioned beneath the ring and contacts a bottom surface of the second ring component. A top surface of the adjustable tuning ring contacts the second ring component. The actuating mechanism is interfaced with the bottom surface of the adjustable tuning ring. The actuating mechanism is configured to actuate the adjustable tuning ring such that the gap between the first ring component and the second ring component varies.

公开(公告)号：US10103010B2

公开(公告)日：2018-10-16

申请号：US15951540

申请日：2018-04-12

Applicant: Applied Materials, Inc.

Inventor： Olivier Luere ,  Leonid Dorf ,  Rajinder Dhindsa ,  Sunil Srinivasan ,  Denis M. Koosau ,  James Rogers

IPC: H01J37/32

Abstract: Embodiments described herein generally related to a substrate processing apparatus. In one embodiment, a process kit for a substrate processing chamber disclosed herein. The process kit includes a first ring having a top surface and a bottom surface, an adjustable tuning ring having a top surface and a bottom surface, and an actuating mechanism. The bottom surface is supported by a substrate support member. The bottom surface at least partially extends beneath a substrate supported by the substrate support member. The adjustable tuning ring is positioned beneath the first ring. The top surface of the adjustable tuning ring and the first ring define an adjustable gap. The actuating mechanism is interfaced with the bottom surface of the adjustable tuning ring. The actuating mechanism is configured to alter the adjustable gap defined between the bottom surface of the first ring and the top surface of the adjustable tuning ring.

公开(公告)号：US09947517B1

公开(公告)日：2018-04-17

申请号：US15382004

申请日：2016-12-16

Applicant: Applied Materials, Inc.

Inventor： Olivier Luere ,  Leonid Dorf ,  Rajinder Dhindsa ,  Sunil Srinivasan ,  Denis M. Koosau ,  James Rogers

IPC: H01J37/32

CPC classification number: H01J37/32642 ,  H01J37/32082 ,  H01J37/32449 ,  H01J37/32513 ,  H01J37/32522 ,  H01J2237/006 ,  H01J2237/334

Abstract: Embodiments described herein generally related to a substrate processing apparatus. In one embodiment, a process kit for a substrate processing chamber disclosed herein. The process kit includes a first ring having a top surface and a bottom surface, an adjustable tuning ring having a top surface and a bottom surface, and an actuating mechanism. The bottom surface is supported by a substrate support member. The bottom surface at least partially extends beneath a substrate supported by the substrate support member. The adjustable tuning ring is positioned beneath the first ring. The top surface of the adjustable tuning ring and the first ring define an adjustable gap. The actuating mechanism is interfaced with the bottom surface of the adjustable tuning ring. The actuating mechanism is configured to alter the adjustable gap defined between the bottom surface of the first ring and the top surface of the adjustable tuning ring.

公开(公告)号：US12237149B2

公开(公告)日：2025-02-25

申请号：US17984772

申请日：2022-11-10

Applicant: Applied Materials, Inc.

Inventor： Deyang Li ,  Sunil Srinivasan ,  Yi-Chuan Chou ,  Shahid Rauf ,  Kuan-Ting Liu ,  Jason A. Kenney ,  Chung Liu ,  Olivier P. Joubert ,  Shreeram Jyoti Dash ,  Aaron Eppler ,  Michael Thomas Nichols

IPC: H01J37/00 ,  H01J37/32

Abstract: Embodiments of the present disclosure generally relate to a system used in a semiconductor device manufacturing process. More specifically, embodiments provided herein generally include apparatus and methods for synchronizing and controlling the delivery of an RF bias signal and a pulsed voltage waveform to one or more electrodes within a plasma processing chamber. The apparatus and methods disclosed herein can be useful to at least minimize or eliminate a microloading effect created while processing small dimension features that have differing densities across various regions of a substrate. The plasma processing methods and apparatus described herein are configured to improve the control of various characteristics of the generated plasma and control an ion energy distribution (IED) of the plasma generated ions that interact with a surface of a substrate during plasma processing. The ability to synchronize and control waveform characteristics of a voltage waveform bias established on a substrate during processing allows for an improved control of the generated plasma and process of forming, for example, high-aspect ratio features in the surface of the substrate by a reactive ion etching process. As a result, greater precision for plasma processing can be achieved, which is described herein in more detail.

公开(公告)号：US20250062131A1

公开(公告)日：2025-02-20

申请号：US18234685

申请日：2023-08-16

Applicant: Applied Materials, Inc.

Inventor： Hanbyul Jin ,  Sangjun Park ,  Menghui Li ,  Xiawan Yang ,  Sunil Srinivasan ,  Meishen Liu ,  Andrew Butler ,  Qian Fu

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311

Abstract: Methods of semiconductor processing may include forming plasma effluents of a plurality of precursors (e.g., an etchant precursor, an oxygen-containing precursor, and a silicon-and-fluorine-containing precursor like silicon tetrafluoride). The plasma effluents may then contact a silicon-containing material and a mask material on a substrate in a processing region of a semiconductor processing chamber. The mask material may have one or more apertures therein that allow the plasma effluents access to the silicon-containing material. Contacting the silicon-containing material and the mask material with the plasma effluents may cause (i) etching the silicon-containing material with the plasma effluents to form and/or deepen one or more features in the silicon-containing material and (ii) simultaneously etching the mask material and depositing a silicon-and-oxygen-containing material on the mask material with the plasma effluents.

公开(公告)号：US11087989B1

公开(公告)日：2021-08-10

申请号：US16905246

申请日：2020-06-18

Applicant: Applied Materials, Inc.

Inventor： Alvaro Garcia De Gorordo ,  Zhonghua Yao ,  Sunil Srinivasan ,  Sang Wook Park

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/311

Abstract: A method for etching silicon at cryogenic temperatures is provided. The method includes forming an inert layer from condensation of a noble gas at cryogenic temperatures on exposed surfaces such as the sidewalls of a feature to passivate the sidewalls prior to the etching process. The method further includes flowing a fluorine-containing precursor gas into the chamber to form a fluorine-containing layer on the inert layer. The method further includes exposing the fluorine-containing layer and the inert layer to an energy source to form a passivation layer on the exposed portions of the substrate and exposing the substrate to ions to etch the substrate.

公开(公告)号：USD797691S1

公开(公告)日：2017-09-19

申请号：US29561163

申请日：2016-04-14

Applicant: Applied Materials, Inc.

Designer： Olivier Joubert ,  Jason A. Kenney ,  Sunil Srinivasan ,  James Rogers ,  Rajinder Dhindsa ,  Vedapuram S. Achutharaman ,  Olivier Luere