公开(公告)号：US09530878B2

公开(公告)日：2016-12-27

申请号：US14935346

申请日：2015-11-06

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/335 ,  H01L29/778 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

公开(公告)号：US09412872B2

公开(公告)日：2016-08-09

申请号：US14521200

申请日：2014-10-22

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, Jr. ,  Ian A. Young ,  Kelin J. Kuhn

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/24 ,  H01L29/267

CPC classification number: H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

Abstract translation: 描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。 例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。 同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。 同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。 栅极堆叠包括栅极电介质部分和栅极电极部分。

公开(公告)号：US20160190345A1

公开(公告)日：2016-06-30

申请号：US15063371

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Van H. Le ,  Benjamin Chu-Kung ,  Harold Hal W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L29/15 ,  H01L29/161

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

公开(公告)号：US20150380557A1

公开(公告)日：2015-12-31

申请号：US14825130

申请日：2015-08-12

Applicant: Intel Corporation

Inventor： Van H. Le ,  Benjamin Chu-Kung ,  Harold Hal W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/283 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

Abstract translation: 提供具有包括压缩和拉伸应变外延材料的交替层的沟道区的晶体管结构。 交替的外延层可以在单和多晶体管结构中形成沟道区。 在替代实施例中，两个交替层中的一个被选择性地蚀刻掉以形成剩余材料的纳米带或纳米线。 得到的应变纳米带或纳米线形成晶体管结构的沟道区。 还提供了包括晶体管的计算设备，晶体管包括由交替的压缩和拉伸应变外延层组成的沟道区，以及包括包含由应变纳米带或纳米线组成的沟道区的晶体管的计算器件。

公开(公告)号：US09209290B2

公开(公告)日：2015-12-08

申请号：US14630541

申请日：2015-02-24

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/338 ,  H01L29/15 ,  H01L29/778 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

公开(公告)号：US08872225B2

公开(公告)日：2014-10-28

申请号：US13722824

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Van Le ,  Robert Chau ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Niti Goel ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Willy Rachmady ,  Marko Radosavljevic ,  Han Wui Then ,  Nancy Zelick

IPC: H01L21/02 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/785

Abstract: An embodiment uses a very thin layer nanostructure (e.g., a Si or SiGe fin) as a template to grow a crystalline, non-lattice matched, epitaxial (EPI) layer. In one embodiment the volume ratio between the nanostructure and EPI layer is such that the EPI layer is thicker than the nanostructure. In some embodiments a very thin bridge layer is included between the nanostructure and EPI. An embodiment includes a CMOS device where EPI layers covering fins (or that once covered fins) are oppositely polarized from one another. An embodiment includes a CMOS device where an EPI layer covering a fin (or that once covered a fin) is oppositely polarized from a bridge layer covering a fin (or that once covered a fin). Thus, various embodiments are disclosed from transferring defects from an EPI layer to a nanostructure (that is left present or removed). Other embodiments are described herein.

Abstract translation: 一个实施例使用非常薄的层纳米结构（例如，Si或SiGe鳍）作为模板来生长晶体，非晶格匹配的外延（EPI）层。 在一个实施方案中，纳米结构和EPI层之间的体积比使得EPI层比纳米结构厚。 在一些实施例中，在纳米结构和EPI之间包括非常薄的桥接层。 一个实施例包括一个CMOS器件，其中覆盖翅片（或一旦被覆盖的翅片）的EPI层彼此相反地极化。 一个实施例包括一个CMOS器件，其中覆盖翅片（或一旦被覆盖的翅片）的EPI层与覆盖翅片（或一旦被覆盖的翅片）的桥接层相反地偏振。 因此，从EPI层转移到纳米结构（剩下的存在或去除）的缺陷中公开了各种实施例。 本文描述了其它实施例。

公开(公告)号：US12183831B2

公开(公告)日：2024-12-31

申请号：US16638301

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Van H. Le ,  Abhishek A. Sharma ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Ravi Pillarisetty ,  Miriam R. Reshotko ,  Shriram Shivaraman ,  Li Huey Tan ,  Tristan A. Tronic ,  Jack T. Kavalieros

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/40 ,  H01L29/417

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US11973143B2

公开(公告)日：2024-04-30

申请号：US16368088

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Benjamin Chu-Kung ,  Subrina Rafique ,  Devin Merrill ,  Ashish Agrawal ,  Harold Kennel ,  Yang Cao ,  Dipanjan Basu ,  Jessica Torres ,  Anand Murthy

IPC: H01L21/84 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

公开(公告)号：US11735670B2

公开(公告)日：2023-08-22

申请号：US17497864

申请日：2021-10-08

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/161 ,  H01L27/088 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

公开(公告)号：US20230057464A1

公开(公告)日：2023-02-23

申请号：US17981561

申请日：2022-11-07

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Aaron D. Lilak ,  Abhishek A. Sharma ,  Van H. Le ,  Seung Hoon Sung ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L27/108 ,  H01L21/822 ,  H01L23/528 ,  H01L49/02 ,  H01L29/06

Abstract: Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.