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    Strained thin film transistors
    31.
    发明授权
    Strained thin film transistors 有权

    公开(公告)号：US11342457B2

    公开(公告)日：2022-05-24

    申请号：US16633094

    申请日：2017-09-18

    Applicant: Intel Corporation

    Inventor： Prashant Majhi ,  Willy Rachmady ,  Brian S. Doyle ,  Abhishek A. Sharma ,  Elijah V. Karpov ,  Ravi Pillarisetty ,  Jack T. Kavalieros

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

    Abstract: Strained thin film transistors are described. In an example, an integrated circuit structure includes a strain inducing layer on an insulator layer above a substrate. A polycrystalline channel material layer is on the strain inducing layer. A gate dielectric layer is on a first portion of the polycrystalline channel material. A gate electrode is on the gate dielectric layer, the gate electrode having a first side opposite a second side. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact on a second portion of the polycrystalline channel material. A second conductive contact adjacent the second side of the gate electrode, the second conductive contact on a third portion of the polycrystalline channel material.

    Thin film tunnel field effect transistors having relatively increased width
    32.
    发明授权
    Thin film tunnel field effect transistors having relatively increased width 有权

    公开(公告)号：US11335705B2

    公开(公告)日：2022-05-17

    申请号：US16631811

    申请日：2017-09-15

    Applicant: Intel Corporation

    Inventor： Prashant Majhi ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Abhishek A. Sharma ,  Elijah V. Karpov

    IPC: H01L27/12 ,  H01L29/423 ,  H01L29/78

    Abstract: Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with a global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.

    Threshold switching contact in a field-effect transistor as a selector
    35.
    发明授权
    Threshold switching contact in a field-effect transistor as a selector 有权

    公开(公告)号：US11152429B2

    公开(公告)日：2021-10-19

    申请号：US15942115

    申请日：2018-03-30

    Applicant: INTEL CORPORATION

    Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Elijah V. Karpov

    IPC: H01L27/24 ,  H01L43/08 ,  H01L27/22 ,  H01L29/786 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78 ,  H01L27/108 ,  H01L43/12 ,  H01L45/00 ,  H01L29/66

    Abstract: An integrated circuit structure includes: a field-effect transistor including a semiconductor region including a semiconductor material having a bandgap less than or equal to that of silicon, a semiconductor source and a semiconductor drain, the semiconductor region being between the semiconductor source and the semiconductor drain, a gate electrode, a gate dielectric between the semiconductor region and the gate electrode, a source contact adjacent to the semiconductor source, and a drain contact adjacent to the semiconductor drain; and a resistive switch or a capacitor electrically connected to the drain contact. One of the source contact and the drain contact includes a threshold switching region, to be a selector for the resistive switch or the capacitor. In some embodiments, the threshold switching region includes a threshold switching oxide or a threshold switching chalcogenide, and the resistive switch or the capacitor is part of a resistive memory cell or capacitive memory cell.

    Perpendicular STTM free layer including protective cap
    36.
    发明授权
    Perpendicular STTM free layer including protective cap 有权

    公开(公告)号：US10950660B2

    公开(公告)日：2021-03-16

    申请号：US16328533

    申请日：2016-09-29

    Applicant: Intel Corporation

    Inventor： Kaan Oguz ,  Kevin P. OBrien ,  Brian S. Doyle ,  Charles C. Kuo ,  Mark L. Doczy

    IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02

    Abstract: A perpendicular spin transfer torque memory (pSTTM) device incorporates a magnetic tunnel junction (MTJ) device having a free magnetic stack and a fixed magnetic stack separated by a dielectric tunneling layer. The free magnetic stack includes an uppermost magnetic layer that is at least partially covered by a cap layer. The cap layer is at least partially covered by a protective layer containing at least one of: ruthenium (Ru); cobalt/iron/boron (CoFeB); molybdenum (Mo); cobalt (Co); tungsten (W); or platinum (Pt). The protective layer is at least partially covered by a cap metal layer which may form a portion of MTJ electrode. The protective layer minimizes the occurrence of physical and/or chemical attack of the cap layer by the materials used in the cap metal layer, beneficially improving the interface anisotropy of the MTJ free magnetic layer.

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