公开(公告)号：US09953959B1

公开(公告)日：2018-04-24

申请号：US15463523

申请日：2017-03-20

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Robert Alan May ,  Yikang Deng ,  Amruthavalli Pallavi Alur ,  Sheng Li ,  Chong Zhang ,  Sri Chaitra Jyotsna Chavali ,  Amanda E. Schuckman

IPC: H01L23/02 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/4817 ,  H01L21/486 ,  H01L25/50 ,  H01L2225/0652 ,  H01L2225/06548

Abstract: A metal protected fan-out cavity enables assembly of a package-on-package (PoP) integrated circuit while reducing PoP solder spacing and overall z-height. A horizontal fan-out conductor provides a contact between a die contact and a lower package via. A metal protection layer may be used during manufacture to protect the fan-out conductor, such as providing a laser stop during laser skiving. The metal protection layer materials and an etching solution may be selected to allow for subsequent removal via etching while leaving the fan-out conductor intact. The metal protection layer and fan-out conductor materials may also be selected to reduce or eliminate formation of an intermetallic compound (IMC) between the metal protection layer and the fan-out conductor.

公开(公告)号：US11830809B2

公开(公告)日：2023-11-28

申请号：US16829336

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ying Wang ,  Yikang Deng ,  Junnan Zhao ,  Andrew James Brown ,  Cheng Xu ,  Kaladhar Radhakrishnan

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L28/10

Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.

公开(公告)号：US11769719B2

公开(公告)日：2023-09-26

申请号：US16017671

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Jonathan Rosch ,  Wei-Lun Jen ,  Cheng Xu ,  Liwei Cheng ,  Andrew Brown ,  Yikang Deng

IPC: H05K1/11 ,  H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/111 ,  H05K1/115 ,  H05K1/025 ,  H05K1/18 ,  H05K2201/095 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09827

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US11705377B2

公开(公告)日：2023-07-18

申请号：US17720202

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Mitul Modi ,  Robert L. Sankman ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Amruthavalli P. Alur ,  Yikang Deng ,  Eric J. Li

IPC: H01L23/13 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L21/4853 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/1432 ,  H01L2924/1434

Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220310512A1

公开(公告)日：2022-09-29

申请号：US17839337

申请日：2022-06-13

Applicant: INTEL CORPORATION

Inventor： Huong Do ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Yikang Deng ,  Amruthavalli P. Alur

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/66 ,  H01L21/768

Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.

公开(公告)号：US20220183157A1

公开(公告)日：2022-06-09

申请号：US17677851

申请日：2022-02-22

Applicant: INTEL CORPORATION

Inventor： Kristof Darmawikarta ,  Robert A. May ,  Yikang Deng ,  Ji Yong Park ,  Maroun D. Moussallem ,  Amruthavalli P. Alur ,  Sri Ranga Sai Boyapati ,  Lilia May

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46

Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.

公开(公告)号：US20210391263A1

公开(公告)日：2021-12-16

申请号：US16902958

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Yikang Deng ,  Wei-Lun Jen ,  Tarek A. Ibrahim ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Yosuke Kanaoka ,  Robin Shea McRee ,  Rahul N. Manepalli

IPC: H01L23/538 ,  H01L21/48

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20210307172A1

公开(公告)日：2021-09-30

申请号：US16321420

申请日：2016-09-02

Applicant: INTEL CORPORATION

Inventor： Kristof Darmawikarta ,  Robert A. May ,  Yikang Deng ,  Ji Yong Park ,  Maroun D. Moussallem ,  Amruthavalli P. Alur ,  Sri Ranga Sai Boyapati ,  Lilia May

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42

Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.

公开(公告)号：US10553453B2

公开(公告)日：2020-02-04

申请号：US16317789

申请日：2016-07-14

Applicant: Intel Corporation

Inventor： Sri Chaitra Chavali ,  Siddharth K. Alur ,  Amanda E. Schuckman ,  Amruthavalli Palla Alur ,  Islam A. Salama ,  Yikang Deng ,  Kristof Darmawikarta

IPC: H05K1/03 ,  H05K3/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimagable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.

公开(公告)号：US20190051447A1

公开(公告)日：2019-02-14

申请号：US16162465

申请日：2018-10-17

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Mihir K. Roy ,  Mathew J. Manusharow ,  Yikang Deng

IPC: H01F27/28 ,  H01F27/255 ,  C25D5/48 ,  H01F41/04 ,  H01F41/02 ,  C25D5/16 ,  H01F17/00 ,  C25D7/00

Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.