公开(公告)号：US20200227469A1

公开(公告)日：2020-07-16

申请号：US16249493

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Zdravko Boos ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Paul B. Fischer

IPC: H01L27/20 ,  H01L29/20 ,  H01L29/78 ,  H01L41/18 ,  H01L25/18 ,  H03F3/195 ,  H03B5/36

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same substrate or die as resonators of RF filters. An example IC structure includes a support structure (e.g., a substrate), a resonator, provided over a first portion of the support structure, and an III-N transistor, provided over a second portion of the support structure. The IC structure includes a piezoelectric material so that first and second electrodes of the resonator enclose a first portion of the piezoelectric material, while a second portion of the piezoelectric material is enclosed between the channel material of the III-N transistor and the support structure. In this manner, one or more resonators of an RF filter may be monolithically integrated with one or more III-N transistors. Such integration may reduce costs and improve performance by reducing RF losses incurred when power is routed off chip.

公开(公告)号：US20200219878A1

公开(公告)日：2020-07-09

申请号：US16243523

申请日：2019-01-09

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Walid M. Hafez

IPC: H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/423 ,  H01L29/786 ,  H01L23/34 ,  H01L29/66 ,  H01L21/8252

Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a TFT provided over a second portion of the III-N material. Because the III-N transistor and the TFT are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the TFT are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration. Integrating TFTs with III-N transistors may reduce costs and improve performance, e.g., by reducing losses incurred when power is routed off chip in a multi-chip package.

公开(公告)号：US10600787B2

公开(公告)日：2020-03-24

申请号：US16078675

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Peter G. Tolchinsky ,  Roza Kotlyar ,  Valluri R. Rao

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8258 ,  H01L23/498 ,  H01L23/544 ,  H01L29/16 ,  H01L29/205 ,  H01L29/423 ,  H01L29/04 ,  H01L29/417 ,  H01L21/8238 ,  H04B1/38

Abstract: This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate.

公开(公告)号：US20200043917A1

公开(公告)日：2020-02-06

申请号：US16489847

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Paul B. Fischer

IPC: H01L27/088 ,  H01L29/20 ,  H01L29/205 ,  H01L21/8252 ,  H01L29/66 ,  H01L29/778

Abstract: Enhancement/depletion device pairs and methods of producing the same are disclosed. A disclosed example multilayered die includes a depletion mode device that includes a first polarization layer and a voltage tuning layer, and an enhancement mode device adjacent the depletion mode device, where the enhancement mode device includes a second polarization layer, and where the second polarization layer includes an opening corresponding to a gate of the enhancement mode device.

公开(公告)号：US10541305B2

公开(公告)日：2020-01-21

申请号：US16246356

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/15 ,  H01L27/088 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/778 ,  H01L29/20 ,  H01L23/66 ,  H01L27/06 ,  H01L29/04 ,  H01L29/205 ,  H01L29/423 ,  H01L21/02

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20190305182A1

公开(公告)日：2019-10-03

申请号：US15940440

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then

IPC: H01L33/20 ,  H01L33/32 ,  H01L33/00 ,  H01L33/10 ,  H01L33/08

Abstract: Micro LED displays offer brighter screens and wider color gamuts than that achievable using traditional LED or OLED displays. Various embodiments are directed to LED and micro LED structures having substrates comprising a metal and oxygen, such as gallium and oxygen, and methods of forming the same. An integrated circuit (IC) structure can include a substrate comprising a metal and oxygen and a core over the substrate. The core can include a group III semiconductor material and nitrogen, and the core can be doped with n-type or p-type dopants. An active layer comprising indium can be provide on a surface of the core. The indium concentration can be adjusted to tune a peak emission wavelength of the IC structure. The IC structure can include a cladding on a surface of the active layer. The cladding can be doped with dopants of opposite type than those used to dope the core.

公开(公告)号：US10411067B2

公开(公告)日：2019-09-10

申请号：US15777511

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic

IPC: H01L21/8238 ,  H01L27/20 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/20 ,  H03H9/05 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L27/092 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L41/187 ,  H01L41/314 ,  H03H3/02 ,  H03H9/17 ,  H03H9/56 ,  H01L29/08 ,  H01L21/762

Abstract: Techniques are disclosed for forming a monolithic integrated circuit semiconductor structure that includes a radio frequency (RF) frontend portion and may further include a CMOS portion. The RF frontend portion includes componentry implemented with column III-N semiconductor materials such as gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and compounds thereof, and the CMOS portion includes CMOS logic componentry implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). Either of the CMOS or RF frontend portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of III-N transistors and/or RF filters, along with column IV CMOS devices on a single substrate. In a more general sense, the techniques can be used for SoC integration of an RF frontend having diverse III-N componentry on a single substrate, in accordance with some embodiments.

公开(公告)号：US20180350911A1

公开(公告)日：2018-12-06

申请号：US16041657

申请日：2018-07-20

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Robert S. Chau

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/778 ,  H01L29/423 ,  H01L29/20

Abstract: The present description relates to n-channel gallium nitride transistors which include a recessed gate electrode, wherein the polarization layer between the gate electrode and the gallium nitride layer is less than about 1 nm. In additional embodiments, the n-channel gallium nitride transistors may have an asymmetric configuration, wherein a gate-to drain length is greater than a gate-to-source length. In further embodiment, the n-channel gallium nitride transistors may be utilized in wireless power/charging devices for improved efficiencies, longer transmission distances, and smaller form factors, when compared with wireless power/charging devices using silicon-based transistors.

公开(公告)号：US20180331224A1

公开(公告)日：2018-11-15

申请号：US16040505

申请日：2018-07-19

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert S. Chau ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Sanaz Gardner ,  Ravi Pillarisetty

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L27/06 ,  H01L21/84 ,  H01L21/02 ,  H01L29/08 ,  H01L21/306 ,  H01L21/762 ,  H01L29/205 ,  H01L29/10 ,  H01L29/20 ,  H01L29/06 ,  H01L29/34

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.

公开(公告)号：US10096683B2

公开(公告)日：2018-10-09

申请号：US15656480

申请日：2017-07-21

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sanaz Gardner ,  Seung Hoon Sung ,  Robert S. Chau

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/20 ,  H01L29/80 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L29/06 ,  H01L29/201 ,  H01L29/778 ,  H01L21/283 ,  H01L29/423

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.