公开(公告)号：US20060125067A1

公开(公告)日：2006-06-15

申请号：US11331969

申请日：2006-01-13

Applicant: James Wehrly ,  Paul Goodwin ,  Russell Rapport

Inventor： James Wehrly ,  Paul Goodwin ,  Russell Rapport

IPC: H01L23/02

CPC classification number: H05K1/189 ,  H05K1/0203 ,  H05K1/11 ,  H05K1/181 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: Provided circuit modules employ flexible circuitry populated with integrated circuitry (ICs). The flex circuitry is disposed about a rigid substrate. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. A strain relief portion of the flex circuitry has preferably fewer layers than the portion of the flex circuitry along which the integrated circuitry is disposed and may further may exhibit more flexibility than the portion of the flex circuit populated with integrated circuitry. The substrate form is preferably devised from thermally conductive materials.

公开(公告)号：US20060108572A1

公开(公告)日：2006-05-25

申请号：US11258438

申请日：2005-10-25

Applicant: James Wehrly

Inventor： James Wehrly

IPC: H01L29/06

CPC classification number: H01L25/50 ,  H01L25/105 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: The present invention provides methods for constructing stacked circuit modules and precursor assemblies with flexible circuitry. Using the methods of the present invention, a single set of flexible circuitry whether articulated as one or two flex circuits may be employed with CSP devices of a variety of configurations either with or without form standards.

Abstract translation: 本发明提供用于构建具有柔性电路的堆叠电路模块和前体组件的方法。 使用本发明的方法，可以将具有铰接为一个或两个柔性电路的单组柔性电路与具有或不具有形式标准的各种配置的CSP装置一起使用。

公开(公告)号：US20060091521A1

公开(公告)日：2006-05-04

申请号：US11316505

申请日：2005-12-21

Applicant: James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Julian Dowden ,  Jeff Buchle

Inventor： James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Julian Dowden ,  Jeff Buchle

IPC: H01L23/48

CPC classification number: H05K1/141 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01087 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734

Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

公开(公告)号：US20050242423A1

公开(公告)日：2005-11-03

申请号：US11175562

申请日：2005-07-05

Applicant: Julian Partridge ,  James Wehrly

Inventor： Julian Partridge ,  James Wehrly

IPC: H01L21/44 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/13 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/01327 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.

Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 在根据本发明的优选实施例中，与一个或多个CSP相关联的形式标准提供了一种物理形式，其允许在广泛的CSP包装系列中发现的许多变化的包装尺寸被利用，同时使用标准连接柔性 电路设计。 在优选实施例中，在CSP和形式标准的组合连接到柔性电路之前，下CSP的触点将被压缩，以在CSP和柔性电路之间形成下部轮廓接触。

公开(公告)号：US20070158800A1

公开(公告)日：2007-07-12

申请号：US11436957

申请日：2006-05-18

Applicant: James Wehrly ,  Ron Orris ,  Leland Szewerenko ,  Tim Roy ,  Julian Partridge ,  David Roper

Inventor： James Wehrly ,  Ron Orris ,  Leland Szewerenko ,  Tim Roy ,  Julian Partridge ,  David Roper

IPC: H01L23/02

CPC classification number: H01L23/13 ,  H01L23/5385 ,  H01L23/5387 ,  H01L25/18 ,  H01L2224/49175 ,  H01L2924/15311 ,  H05K1/147 ,  H05K1/182 ,  H05K1/189 ,  H05K3/326 ,  H05K2201/056 ,  H05K2201/091 ,  H05K2201/10515 ,  H05K2201/10689

Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

Abstract translation: 本发明提供一种用于使用柔性电路组合引线封装IC和半导体管芯以减少组合的覆盖区的系统和方法。 引线IC封装沿柔性电路的正面设置。 在优选实施例中，引线IC封装的引线被配置为允许引线IC封装的主体的下表面通过粘合剂直接或间接地接触柔性电路的表面。 半导体管芯连接到柔性电路的反面。 在一个实施例中，半导体管芯设置在柔性反面的另一侧，而在替代实施例中，将半导体管芯设置在柔性电路中的窗口中，以直接或间接地安置在引线IC封装体上。 模块触点以各种配置提供。 在优选实施例中，引线IC封装是闪存，半导体管芯是控制器。

公开(公告)号：US20070080470A1

公开(公告)日：2007-04-12

申请号：US11248662

申请日：2005-10-11

Applicant: James Wehrly ,  David Roper

Inventor： James Wehrly ,  David Roper

IPC: H01L23/48

CPC classification number: H05K1/147 ,  H01L23/49827 ,  H01L23/5387 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/189 ,  H05K3/3421 ,  H05K2201/049 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A system and method for electrically and thermally coupling adjacent IC packages to one another in a stacked configuration is provided. A flex circuit is inserted in part between ICs to be stacked and provides a connective field that provides plural contact areas that connect to respective leads of the ICs. Thus, the flex does not require discrete leads which must be individually aligned with the individual leads of the constituent ICs employed in the stack. The principle may be employed to aggregate two or more contact areas for respective connection to leads of constituent ICs but is most profitably employed with a continuous connective field that provides contact areas for many leads of the ICs.

公开(公告)号：US20060255446A1

公开(公告)日：2006-11-16

申请号：US11403081

申请日：2006-04-12

Applicant: James Wehrly

Inventor： James Wehrly

IPC: H01L23/48 ,  H01L21/68

CPC classification number: H01L25/105 ,  H01L21/4871 ,  H01L23/3114 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5387 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/3511 ,  Y10T29/49169 ,  Y10T29/53209 ,  Y10T29/5327 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a precursor assembly devised as a component for a stacked circuit module in accordance with a preferred embodiment of the present invention, one or more stiffeners are disposed at least partially between a flex circuit and an integrated circuit. In a two-high stacked circuit module devised in accordance with a preferred embodiment of the present invention, an integrated circuit is stacked above a precursor assembly. The two integrated circuits are connected with the flex circuit of the precursor assembly. The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules.

Abstract translation: 本发明将集成电路堆叠成节省电路板表面积的模块。 在根据本发明的优选实施例设计为用于堆叠电路模块的部件的前驱体组件中，一个或多个加强件至少部分地设置在柔性电路和集成电路之间。 在根据本发明的优选实施例设计的两层叠层电路模块中，集成电路堆叠在前体组件的上方。 两个集成电路与前体组件的柔性电路连接。 本发明可以有益于模块中集成电路的多种配置和组合。

公开(公告)号：US20060090102A1

公开(公告)日：2006-04-27

申请号：US11283355

申请日：2005-11-18

Applicant: James Wehrly ,  James Wilder ,  Mark Wolfe ,  Paul Goodwin

Inventor： James Wehrly ,  James Wilder ,  Mark Wolfe ,  Paul Goodwin

IPC: G06F11/00

CPC classification number: H05K1/189 ,  H05K1/0203 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of major sides. Contacts are distributed along the flexible circuitry to provide connection between the module and an application environment. The populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on one or both sides of the substrate with one or more layers of integrated circuitry on one or both sides of the substrate. The substrate form is preferably devised from thermally-conductive materials and one or more thermal spreaders are disposed in thermal contact with at least some of the constituent integrated circuitry of the module. Optionally, as an additional thermal management feature, the module may include a high thermal conductivity thermal sink or area that is disposed proximal to, higher thermal energy IC devices. In preferred embodiments, extensions from the substrate body or substrate core encourage reduced thermal variations amongst the ICs of the module while providing an enlarged surface for shedding thermal energy from the module.

Abstract translation: 灵活的电路装有沿主要侧面或两侧设置的集成电路（IC）。 触点沿柔性电路分布，以提供模块与应用环境之间的连接。 填充的柔性电路围绕刚性衬底的边缘设置，从而将集成电路放置在衬底的一侧或两侧上，在衬底的一侧或两侧上具有一层或多层集成电路。 衬底形式优选地由导热材料设计，并且一个或多个热扩散器设置成与模块的组成集成电路中的至少一些热接触。 可选地，作为附加的热管理特征，模块可以包括设置在较高热能IC器件附近的高导热性散热器或区域。 在优选实施例中，来自衬底主体或衬底芯的延伸部促进模块的IC之间的热变化减小，同时提供用于从模块中排出热能的放大表面。

公开(公告)号：US20060050592A1

公开(公告)日：2006-03-09

申请号：US11187269

申请日：2005-07-22

Applicant: James Cady ,  James Wehrly ,  Paul Goodwin

Inventor： James Cady ,  James Wehrly ,  Paul Goodwin

IPC: G11C8/00

CPC classification number: H05K1/189 ,  H05K2201/056 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: A flexible circuit is populated on one or both sides and disposed about a substrate to create a circuit module. Along one of its edges, the flex circuit is connected to a connective facility such as a multiple pin connector while the flex circuit is disposed about a thermally-conductive form that provides structure to create a module with plural layers of circuitry in a single module. In preferred embodiments, the form is metallic and, in alternative preferred embodiments, the module circuitry is disposed within a housing. Preferred embodiments may be devised that present a compact flash module within a housing that may be connected to or into a system or product through a connective facility that is preferably a male or female socket connector while the housing is configured to mechanically adapt to an application environment.

公开(公告)号：US20060048385A1

公开(公告)日：2006-03-09

申请号：US11242962

申请日：2005-10-04

Applicant: James Cady ,  James Wehrly ,  Paul Goodwin

Inventor： James Cady ,  James Wehrly ,  Paul Goodwin

IPC: H01R43/02

CPC classification number: G11C5/143 ,  G11C5/04 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/1572 ,  Y10T29/4913 ,  Y10T29/49179 ,  H01L2924/00

Abstract: Flexible circuitry is populated on one or both sides with integrated circuits (ICs) each of which ICs has an IC profile (height). A substantially flat, windowed fixture with a fixture profile less than the IC profiles of the ICs is applied over an IC-populated side of the flexible circuitry causing at least a part of the ICs to emerge from respective fixture windows. Material is removed simultaneously from that portion of the ICs that emerge from the windows to result in lower-profile ICs which, in a preferred embodiment exhibit profiles substantially coincident with the fixture profile established by the upper surface of the fixture. The method is used to advantage in devising circuit modules by disposing the flexible circuitry about a rigid substrate to form the circuit module with a low profile. Some embodiments use substrates that are windowed or have inset areas into which the lower profile CSPs may be set to reach profile requirements.

Abstract translation: 灵活的电路在一侧或两侧安装集成电路（IC），每个IC都具有IC配置文件（高度）。 具有小于IC的IC轮廓的夹具轮廓的基本平坦的窗口固定件被施加在柔性电路的IC填充侧上，导致至少一部分IC从相应的固定窗口出来。 从窗口出现的IC的那部分同时移除材料以产生较小轮廓的IC，其在优选实施例中表现出与由固定装置的上表面确定的夹具轮廓基本一致的轮廓。 该方法用于通过将柔性电路围绕刚性衬底设置以形成具有低轮廓的电路模块来设计电路模块。 一些实施例使用被窗口化或具有插入区域的衬底，下部轮廓CSP可设置到其中以达到轮廓要求。