公开(公告)号：US20190163363A1

公开(公告)日：2019-05-30

申请号：US15867719

申请日：2018-01-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Lih Yuarn Ou ,  Szu-Wei Chen

IPC: G06F3/06 ,  G11C16/26 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G11C16/0483 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0407

Abstract: A data accessing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; reading the first physical programming unit by using a second read voltage to obtain second data; inputting a first state parameter corresponding to the first data and a second state parameter corresponding to the second data into a numerical calculation engine, and determining a third reading voltage for reading the first physical programming unit by the numerical calculation engine.

公开(公告)号：US10074433B1

公开(公告)日：2018-09-11

申请号：US15786604

申请日：2017-10-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Cheng Hsu ,  Wei Lin ,  Yu-Siang Yang

IPC: G11C7/00 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C7/10

CPC classification number: G11C16/107 ,  G11C7/1006 ,  G11C7/1045 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

Abstract: A data encoding method, a memory control circuit unit and a memory storage device are provided. The method includes: writing a first data into a first physical programming unit of a first physical programming unit group among a plurality of physical programming unit groups; writing a second data into a second physical programming unit of a second physical programming unit group among the plurality of physical programming unit groups; encoding the first data and the second data to generate an encoded data; and writing the encoded data into a third physical programming unit group among the plurality of physical programming unit groups.

公开(公告)号：US09812194B1

公开(公告)日：2017-11-07

申请号：US15481473

申请日：2017-04-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/08

CPC classification number: G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3495

Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining usage state information of first memory cells; reading second memory cells by a first read voltage level to obtain at least one first bit and reading the second memory cells by a second read voltage level to obtain at least one second bit according to the usage state information, wherein the first bit corresponds to a storage state of a first part of memory cells among the second memory cells, the second bit corresponds to a storage state of a second part of memory cell among the second memory cells, and the first read voltage level is different from the second read voltage level; and decoding third bits including the first bit and the second bit. Therefore, a decoding efficiency can be improved.

公开(公告)号：US09715429B1

公开(公告)日：2017-07-25

申请号：US15249487

申请日：2016-08-29

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin

IPC: G11C11/34 ,  G06F11/10 ,  G11C16/26 ,  G11C16/10 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: reading first data from a plurality of first memory cells of a rewritable non-volatile memory module based on a first read voltage level and performing a first decoding operation; estimating a channel status of the rewritable non-volatile memory module and obtaining a second read voltage level according to the channel status if the first decoding operation fails, and the second read voltage level is different from the first read voltage level, and the second read voltage level is different from an optimal read voltage level; and reading second data from the plurality of first memory cells based on the second read voltage level and performing a second decoding operation. Therefore, an encoding efficiency can be improved.

公开(公告)号：US09582224B2

公开(公告)日：2017-02-28

申请号：US14702768

申请日：2015-05-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Kuo-Hsin Lai ,  Tien-Ching Wang

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/34

CPC classification number: G06F3/0688 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/34

Abstract: A memory control circuit unit including a plurality of data randomizer circuits and a data selection circuit is provided. When a first data stream is received from a host system, the first data stream is input into the data randomizer circuits to respectively output a plurality of second data streams. The data selection circuit selects one of the second data streams as a third data stream according to contents of the second data streams, and the third data stream is programmed into a rewritable non-volatile memory module. Accordingly, data written into the rewritable non-volatile memory module can be effectively disarranged.

Abstract translation: 提供包括多个数据随机化器电路和数据选择电路的存储器控​​制电路单元。 当从主机系统接收到第一数据流时，将第一数据流输入到数据随机化器电路中，以分别输出多个第二数据流。 数据选择电路根据第二数据流的内容选择第二数据流中的一个作为第三数据流，并将第三数据流编程到可重写的非易失性存储器模块中。 因此，写入可重写非易失性存储器模块的数据可以被有效地排除。

公开(公告)号：US09529666B2

公开(公告)日：2016-12-27

申请号：US14295355

申请日：2014-06-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Siu-Tung Lam

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/42 ,  H03M13/37 ,  H03M13/00 ,  H03M13/11 ,  H03M13/15 ,  H03M13/23

CPC classification number: G06F11/1008 ,  G06F11/1012 ,  G11C29/42 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/23 ,  H03M13/3715 ,  H03M13/3723 ,  H03M13/6325

Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路。 解码方法包括：发送配置为读取存储单元的读命令序列，以获得多个第一验证位; 执行根据所述第一验证比特的第一解码过程，以及确定是否生成第一有效码字; 如果不产生第一有效码字，则发送另一读取命令序列，被配置为获得多个第二验证比特; 根据第二验证位计算符合特定条件的存储单元的总数; 根据总数获取信道可靠性消息; 以及根据信道可靠性消息执行第二解码过程。 因此，可以提高解码的校正能力。

公开(公告)号：US09514819B2

公开(公告)日：2016-12-06

申请号：US14529166

申请日：2014-10-31

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Kiang-Giap Lau

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3427

Abstract: A programming method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a first write command; and selecting a first physical erasing unit and sending a first skipping write command sequence according to the first write command. The first skipping write command sequence instructs to execute a first skipping programming process. The first skipping programming process includes: programming first data into a first word line of the first physical erasing unit; and after the first word line is programmed, skipping a second word line adjacent to the first word line, and programming the first data into a third word line not adjacent to the first word line.

Abstract translation: 提供编程方法，存储器存储装置和存储器控制电路单元。 该方法包括：接收第一写命令; 以及选择第一物理擦除单元并根据第一写入命令发送第一跳过写入命令序列。 第一个跳过写入命令序列指示执行第一次跳过编程过程。 第一跳过编程过程包括：将第一数据编程到第一物理擦除单元的第一字线中; 并且在第一字线被编程之后，跳过与第一字线相邻的第二字线，并将第一数据编程成不与第一字线相邻的第三字线。

公开(公告)号：US20160247575A1

公开(公告)日：2016-08-25

申请号：US14682123

申请日：2015-04-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G11C16/26 ,  G11C29/52 ,  G06F11/10 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G11C7/1006 ,  G11C2029/0411

Abstract: A data reading method is provided. The data reading method includes receiving a read command from a host system; sending a first read command sequence to obtain a first data string from memory cells of a rewritable non-volatile memory module; performing a decoding procedure on the first data string to generate a decoded first data string; and, if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data string from the memory cells, performing a logical operation on the decoded first data string and the second data string to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted first data string as the decoded first data string.

Abstract translation: 提供了一种数据读取方法。 数据读取方法包括从主机系统接收读取命令; 发送第一读取命令序列以从可重写非易失性存储器模块的存储器单元获得第一数据串; 对所述第一数据串执行解码过程以生成解码的第一数据串; 并且如果在解码的第一数据串中存在错误位，则从存储器单元发送第二读取命令序列以获得第二数据串，对解码的第一数据串和第二数据串执行逻辑运算以获得 调整数据串，根据调整数据串调整解码后的第一数据串，得到经调整后的第一数据串，并使用对经过调整的第一数据串进行解码过程后获得的数据串作为解码后的第一数据串。

公开(公告)号：US09396804B1

公开(公告)日：2016-07-19

申请号：US14854056

申请日：2015-09-15

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin

IPC: G11C16/00 ,  G11C16/14 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C8/12 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/16

Abstract: A memory programming method for a physical erasing unit of a rewritable non-volatile memory is provided. The method includes: programming a first data stream into a first physical programming unit, wherein the first physical programming unit is constituted by memory cells at intersection of a first bit line set of the physical erasing unit and a first word line layer of the physical erasing unit. The method further includes: after programming the first data stream into the first physical programming unit, programming another data stream into another physical programming unit, and the another physical programming unit is constituted by the memory cells at intersection of the first bit line set of the physical erasing unit and another word line layer of the physical erasing unit.

Abstract translation: 提供了一种用于可重写非易失性存储器的物理擦除单元的存储器编程方法。 该方法包括：将第一数据流编程到第一物理编程单元中，其中第一物理编程单元由物理擦除单元的第一位线组和物理擦除的第一字线层的交叉处的存储单元构成 单元。 该方法还包括：在将第一数据流编程到第一物理编程单元之后，将另一个数据流编程到另一个物理编程单元中，另一个物理编程单元由位于第一物理编程单元的第一位线组 物理擦除单元和物理擦除单元的另一个字线层。

公开(公告)号：US20160188213A1

公开(公告)日：2016-06-30

申请号：US14636191

申请日：2015-03-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu

IPC: G06F3/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/12

CPC classification number: G11C16/3459 ,  G11C5/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3404 ,  G11C29/52 ,  G11C2029/0411

Abstract: A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method includes: programming data into a plurality of memory cells of a rewritable non-volatile memory module; determining whether a storage state of the data conforms with a first condition or a second condition based on a default bias range and a threshold voltage distribution of the memory cells storing the data; performing a first operation if the storage state of the data conforms with the first condition; and performing a second operation if the storage state of the data conforms with the second condition. Accordingly, the probability of misidentifying the valid data as the invalid data may be reduced.

Abstract translation: 提供存储器管理方法，存储器存储装置和存储器控制电路单元。 该方法包括：将数据编程到可重写非易失性存储器模块的多个存储单元中; 基于存储数据的存储单元的默认偏置范围和阈值电压分布来确定数据的存储状态是否符合第一条件或第二条件; 如果数据的存储状态符合第一条件，则执行第一操作; 以及如果所述数据的存储状态符合所述第二条件，则执行第二操作。 因此，可以减少将有效数据误认为无效数据的概率。