公开(公告)号：US10741410B2

公开(公告)日：2020-08-11

申请号：US15726040

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Joy Cheng ,  Ching-Yu Chang

IPC: H01L21/3213 ,  C08F12/08 ,  G03F7/025 ,  G03F7/027 ,  G03F7/075 ,  G03F7/004 ,  G03F7/038 ,  G03F7/029 ,  G03F7/09 ,  G03F7/033 ,  C08K5/00 ,  C08K3/011

Abstract: Provided is a material composition and method for that includes providing a substrate and forming a resist layer over the substrate. In various embodiments, the resist layer includes a metal complex including a radical generator, an organic core, and an organic solvent. By way of example, the organic core includes at least one cross-linker site. In some embodiments, an exposure process is performed to the resist layer. After performing the exposure process, the exposed resist layer is developed to form a patterned resist layer.

公开(公告)号：US10698317B2

公开(公告)日：2020-06-30

申请号：US15903796

申请日：2018-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Wei-Han Lai ,  Ching-Yu Chang

IPC: G03F7/20 ,  G03F7/16 ,  G03F7/09 ,  G03F7/075 ,  G03F7/11 ,  G03F7/095 ,  H01L21/033 ,  H01L21/027

Abstract: A method includes providing a layered structure on a substrate, the layered structure including a bottom layer formed over the substrate, a hard mask layer formed over the bottom layer, a material layer formed over the hard mask layer, and a photoresist layer formed over the material layer, exposing the photoresist layer to a radiation source, developing the photoresist layer, where the developing removes portions of the photoresist layer and the material layer in a single step without substantially removing portions of the hard mask layer, and etching the hard mask layer using the photoresist layer as an etch mask. The material layer may include acidic moieties and/or acid-generating molecules. The material layer may also include photo-sensitive moieties and crosslinking agents.

公开(公告)号：US10658184B2

公开(公告)日：2020-05-19

申请号：US15474522

申请日：2017-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Chi-Cheng Hung ,  Chin-Hsiang Lin ,  Chien-Wei Wang ,  Ching-Yu Chang ,  Chih-Yuan Ting ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yuan-Hsiang Lung ,  Yen-Ming Chen ,  Yung-Sung Yen

IPC: H01L21/265 ,  H01L21/311 ,  H01L21/033

Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.

公开(公告)号：US10517179B2

公开(公告)日：2019-12-24

申请号：US15621646

申请日：2017-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan Wang ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  H05K3/06 ,  G03F7/09 ,  G03F7/00 ,  G03F7/20 ,  G03F7/40

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate. The patterned resist layer has a first pattern width, and the patterned resist layer has a first pattern profile having a first proportion of active sites. In some examples, the patterned resist layer is coated with a treatment material. In some embodiments, the treatment material bonds to surfaces of the patterned resist layer to provide a treated patterned resist layer having a second pattern profile with a second proportion of active sites greater than the first proportion of active sites. By way of example, and as part of the coating the patterned resist layer with the treatment material, a first pattern shrinkage process may be performed, where the treated patterned resist layer has a second pattern width less than a first pattern width.

公开(公告)号：US10515812B1

公开(公告)日：2019-12-24

申请号：US16102347

申请日：2018-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Wang ,  Joy Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/00 ,  H01L21/288 ,  H01L21/3213

Abstract: A method includes forming a metal-containing material layer over a substrate, patterning the metal-containing material layer, where the patterned material layer has an average roughness, and electrochemically treating the patterned metal-containing material layer to reduce the average roughness. The treatment may be implemented by exposing the patterned metal-containing material layer to an electrically conducting solution, and applying a potential between the patterned material layer and a counter electrode exposed to the solution, such that the treating reduces the average roughness of the patterned material layer. The electrically conducting solution may include an ionic compound dissolved in water, alcohol, and/or a surfactant.

公开(公告)号：US20190385816A1

公开(公告)日：2019-12-19

申请号：US16007780

申请日：2018-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Shun Hsu ,  Ching-Yu Chang ,  Chiao-Kai Chang ,  Wai Hong Cheah ,  Chien-Fang Lin

IPC: H01J37/32 ,  H01L21/66 ,  H01L21/67

Abstract: An embodiment is an apparatus, such as a plasma chamber. The apparatus includes chamber walls and a chamber window defining an enclosed space. A chamber window is disposed between a plasma antenna and a substrate support. A gas delivery source is mechanically coupled to the chamber window. The gas delivery source comprises a gas injector having a passageway, a window at a first end of the passageway, and a nozzle at a second end of the passageway. The nozzle of the gas delivery source is disposed in the enclosed space. A fastening device is mechanically coupled to the gas delivery source. The fastening device is adjustable to adjust a sealing force against the gas injector.

公开(公告)号：US20180341177A1

公开(公告)日：2018-11-29

申请号：US15694222

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Liu ,  Wei-Han Lai ,  Tzu-Yang Lin ,  Ming-Hui Weng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/32

CPC classification number: G03F7/325 ,  G03F7/038 ,  G03F7/16 ,  G03F7/20 ,  G03F7/2004

Abstract: The present disclosure provides NTD developers and corresponding lithography techniques that can overcome resolution, line edge roughness (LER), and sensitivity (RLS) tradeoff barriers particular to extreme ultraviolet (EUV) technologies, thereby achieving high patterning fidelity for advanced technology nodes. An exemplary lithography method includes forming a negative tone resist layer over a workpiece; exposing the negative tone resist layer to EUV radiation; and removing an unexposed portion of the negative tone resist layer in a negative tone developer, thereby forming a patterned negative tone resist layer. The negative tone developer includes an organic solvent having a log P value greater than 1.82. The organic solvent is an ester acetate derivative represented by R1COOR2. R1 and R2 are hydrocarbon chains having four or less carbon atoms. In some implementations, R1, R2, or both R1 and R2 are propyl functional groups, such as n-propyl, isopropyl, or 2-methylpropyl.

公开(公告)号：US10115585B2

公开(公告)日：2018-10-30

申请号：US15628261

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Liu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: C08G77/16 ,  H01L21/02 ,  H01L21/308 ,  H01L21/033 ,  C08G77/52 ,  C08G77/00

Abstract: Provided is a material composition and method for that includes forming a silicon-based resin over a substrate. In various embodiments, the silicon-based resin includes a nitrobenzyl functional group. In some embodiments, a baking process is performed to cross-link the silicon-based resin. Thereafter, the cross-linked silicon-based resin is patterned and an underlying layer is etched using the patterned cross-linked silicon-based resin as an etch mask. In various examples, the cross-linked silicon-based resin is exposed to a radiation source, thereby de-cross-linking the silicon-based resin. In some embodiments, the de-cross-linked silicon-based resin is removed using an organic solution.

公开(公告)号：US10083832B1

公开(公告)日：2018-09-25

申请号：US15468109

申请日：2017-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Liu ,  Chin-Hsiang Lin ,  Ching-Yu Chang ,  Ming-Hui Weng

IPC: H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  C09D201/06 ,  G03F7/11 ,  G03F7/16 ,  G03F7/09

Abstract: Under layer composition and methods of manufacturing semiconductor devices are disclosed. The method of manufacturing semiconductor device includes the following steps. A layer of an under layer composition is formed, wherein the under layer composition includes a polymeric material and a cross-linker, and the cross-linker includes at least one decomposable functional group. A curing process is performed on the layer of the under layer composition to form an under layer, wherein the cross-linker is crosslinked with the polymeric material to form a crosslinked polymeric material having the at least one decomposable functional group. A patterned photoresist layer is formed over the under layer. An etching process is performed to transfer a pattern of the patterned photoresist layer to the under layer. The under layer is removed by decomposing the decomposable functional group.

公开(公告)号：US10073347B1

公开(公告)日：2018-09-11

申请号：US15685908

申请日：2017-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Joy Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/039 ,  G03F7/20 ,  H01L21/027 ,  H01L21/02 ,  G03F7/16 ,  H01L21/67

CPC classification number: G03F7/2028 ,  G03F7/0392 ,  G03F7/162 ,  G03F7/38 ,  G03F7/40 ,  H01L21/02282 ,  H01L21/0274 ,  H01L21/6715

Abstract: The present disclosure provides a method that includes coating an edge portion of a wafer by a first chemical solution including a chemical mixture of an acid-labile group, a solubility control unit and a thermal acid generator; curing the first chemical solution to form a first protecting layer on the edge portion of the wafer; coating a resist layer on a front surface of the wafer; removing the first protecting layer by a first removing solution; and performing an exposing process to the resist layer.