公开(公告)号：US20250105059A1

公开(公告)日：2025-03-27

申请号：US18471823

申请日：2023-09-21

Applicant: Tokyo Electron Limited

Inventor： Ryota Yonezawa ,  Kai-Hung Yu ,  Ying Trickett ,  Hidenao Suzuki

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532

Abstract: A method of processing a substrate includes exposing the substrate to a boron-containing precursor to adsorb over the substrate, where the substrate includes a dielectric layer formed over a conductive layer, and the conductive layer is exposed at a bottom of a recess formed in the dielectric layer. The method includes exposing the adsorbed boron-containing precursor to a plasma and filling the recess with a conductive fill material bottom up by a vapor deposition process, where a vertical deposition rate of the conductive fill material is greater than a lateral deposition rate of the conductive fill material.

公开(公告)号：US20240363410A1

公开(公告)日：2024-10-31

申请号：US18620326

申请日：2024-03-28

Applicant: Tokyo Electron Limited

Inventor： Ryota Yonezawa ,  Kai-Hung Yu ,  Yuji Otsuki ,  Kenichi Imakita ,  Atsushi Gomi ,  Kohichi Satoh ,  Tadahiro Ishizaka ,  Takashi Sakuma ,  Hidenao Suzuki

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L21/76805

Abstract: A method for forming a semiconductor device can include providing a substrate including a via in a dielectric layer, forming a ruthenium metal plug in the via, and at least part of the ruthenium metal plug can be formed directly on the dielectric layer in the via, forming a metal cap layer directly on the ruthenium metal plug, and forming a metallization layer, such as a copper-containing trench, over the ruthenium metal plug, such that the metal cap layer is between the metallization layer and the ruthenium metal plug, which can prevent intermixing of the ruthenium of the ruthenium metal plug with the metal or metals in the metallization layer.

公开(公告)号：US20240178003A1

公开(公告)日：2024-05-30

申请号：US18070030

申请日：2022-11-28

Applicant: Tokyo Electron Limited

Inventor： Hirokazu Aizawa ,  Kai-Hung Yu ,  Nicholas Joy ,  Yusuke Yoshida ,  Kandabara Tapily

IPC: H01L21/3213 ,  G03F7/20 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3205

CPC classification number: H01L21/32133 ,  G03F7/70733 ,  H01L21/02164 ,  H01L21/02263 ,  H01L21/02318 ,  H01L21/0337 ,  H01L21/32051 ,  H01L21/32055

Abstract: A method for processing a substrate that includes: depositing a filling material over the substrate including a first recess and a second recess, the filling material filling the first recess and the second recess; patterning the filling material such that the first recess is reopened while the second recess remains filled with the filling material; filling the first recess with a conductive material to a first height; etching the filling material selectively to the conductive material to reopen the second recess; filling a remainder of the first recess and the second recess with the conductive material; and performing an etch back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to a second height.

公开(公告)号：US20230343598A1

公开(公告)日：2023-10-26

申请号：US17726992

申请日：2022-04-22

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  Andrew Metz ,  Yun Han ,  Minjoon Park ,  Kai-Hung Yu ,  Eric Chih-Fang Liu

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L25/065

CPC classification number: H01L21/3081 ,  H01L21/0337 ,  H01L21/0228 ,  H01L21/31144 ,  H01L21/32139 ,  H01L25/0657 ,  H01L27/11556

Abstract: Various embodiments of stacked structures, process steps and methods are provided herein for etching high aspect ratio features (e.g., contact holes, vias, trenches, etc.) within a stacked structure comprising a hard mask layer, which is formed above and in contact with one or more underlying layers. At least one etch stop layer (ESL) is provided within the hard mask layer to divide the hard mask layer into two or more distinct portions. When the stacked structure is subsequently etched to form high aspect ratio features within the hard mask layer, such as contact holes or vias that extend through the hard mask layer, the ESL(s) included within the hard mask layer improve etch rate and critical dimension (CD) uniformity of the features etched within the hard mask layer.

公开(公告)号：US20230274932A1

公开(公告)日：2023-08-31

申请号：US18156142

申请日：2023-01-18

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Robert D. Clark ,  Ryota Yonezawa ,  Hiroaki Niimi ,  Hidenao Suzuki ,  Kandabara Tapily ,  Takahiro Miyahara ,  Cory Wajda

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L21/0228 ,  H01L21/76879

Abstract: A method for processing a substrate includes treating the substrate with a small molecular inhibitor (SMI), the substrate including a recess formed in a dielectric layer and a first metal layer in the recess, the SMI covering a surface of the first metal layer. The method further includes, after treating the substrate with the SMI, treating the substrate with a large molecular inhibitor (LMI), the LMI covering sidewalls of the dielectric layer in the recess. The method further includes heating the substrate to remove the SMI from the first metal layer and to expose the first metal layer in the recess, where the LMI remains on the sidewalls after removing the SMI from the first metal layer. The method further includes depositing a second metal over the first metal layer in the recess, where the LMI covering the sidewalls prevents deposition of the second metal on the dielectric layer.

公开(公告)号：US20220319838A1

公开(公告)日：2022-10-06

申请号：US17220025

申请日：2021-04-01

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Angelique Raley ,  Kai-Hung Yu

IPC: H01L21/027 ,  G03F7/09 ,  H01L21/311

Abstract: A substrate is provided with a patterned layer, such as, a photo resist layer which may exhibit line roughness. The patterned layer may be an EUV photo resist layer utilized in a self-aligned multi-patterning process. A tone inversion process having a tone inversion layer is utilized along with a surface treatment of a sidewall of the tone inversion layer so as to improve line roughness characteristics of the process. More specifically, a tone inversion layer may be patterned and then sidewalls of the tone inversion layer may be treated. A fill material may then be deposited upon the substrate including adjacent the sidewalls of the tone inversion layer. When the tone inversion layer is removed, the roughness of the fill material will be reduced due to the use of the sidewall treatment.

公开(公告)号：US20220139776A1

公开(公告)日：2022-05-05

申请号：US17507136

申请日：2021-10-21

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  David L. O'Meara ,  Hisashi Higuchi ,  Hirokazu Aizawa ,  Omid Zandi ,  Cory Wajda ,  Gerrit J. Leusink

IPC: H01L21/768 ,  H01L21/285

Abstract: A method for filling recessed features with a low-resistivity metal includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, and depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature. The method further includes removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature, where the removing includes exposing the patterned substrate to an etching gas containing ozone.

公开(公告)号：US10950444B2

公开(公告)日：2021-03-16

申请号：US16252949

申请日：2019-01-21

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Kai-Hung Yu ,  Andrew Metz

IPC: H01L21/00 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311

Abstract: Embodiments are disclosed for a method to process microelectronic workpieces including forming a metal hard mask layer including ruthenium (Ru MHM layer) over one or more underlying layers on a substrate for a microelectronic workpiece, etching the Ru MHM layer to provide a patterned Ru MHM layer, and etching the one or more underlying layers using the patterned Ru MHM layer as a mask to protect portion of the one or more underlying layers. For one embodiment, the Ru MHM layer is a material including 95 percent or more of ruthenium (Ru). For another embodiment, the Ru MHM layer is a material including 70 percent or more of ruthenium (Ru). Further, the Ru MHM layer preferably has a selectivity of 10 or greater with respect to a next underlying layer adjacent to the Ru MHM layer, such as a SiN hard mask layer.

公开(公告)号：US10886173B2

公开(公告)日：2021-01-05

申请号：US16357721

申请日：2019-03-19

Applicant: Tokyo Electron Limited

Inventor： Robert Clark ,  Kandabara Tapily ,  Kai-Hung Yu

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  H01L21/677 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  G05B13/02 ,  G05B19/418 ,  C23C14/24 ,  C23C14/34 ,  H01J37/32

Abstract: A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.

公开(公告)号：US20190295890A1

公开(公告)日：2019-09-26

申请号：US16357721

申请日：2019-03-19

Applicant: Tokyo Electron Limited

Inventor： Robert Clark ,  Kandabara Tapily ,  Kai-Hung Yu

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/285 ,  H01L21/02

Abstract: A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.