公开(公告)号：US12288692B2

公开(公告)日：2025-04-29

申请号：US17721014

申请日：2022-04-14

Applicant: TOKYO ELECTRON LIMITED

Inventor： Yun Han ,  Alok Ranjan ,  Peter Ventzek ,  Andrew Metz ,  Hiroaki Niimi

IPC: H01L21/285 ,  H01L21/02 ,  H10D30/01 ,  H10D30/62 ,  H10D64/01 ,  H10D64/62

Abstract: A method for manufacturing a FET semiconductor structure includes providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET. A TiSi2 film with C54 structure is selectively deposited directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate. The dummy gate is replaced with a replacement metal gate.

公开(公告)号：US20250046617A1

公开(公告)日：2025-02-06

申请号：US18362608

申请日：2023-07-31

Applicant: Tokyo Electron Limited

Inventor： Adam Pranda ,  Yusuke Yoshida ,  Aelan Mosden ,  Yun Han

IPC: H01L21/311 ,  H01J37/32 ,  H01L29/66

Abstract: A method of processing a substrate that includes: forming a bottom passivation layer including an oxide over a first portion of a dielectric layer at a bottom of a recess of the substrate, the recess having sidewalls including a second portion of the dielectric layer; and performing a lateral etch to etch the second portion of the dielectric layer, the bottom passivation layer covering the first portion of the dielectric layer during the lateral etch, and where the forming of the bottom passivation layer includes exposing the substrate to a first plasma including a halogen, and exposing the substrate to a second plasma including oxygen to form the bottom passivation layer.

公开(公告)号：US12040176B2

公开(公告)日：2024-07-16

申请号：US17706408

申请日：2022-03-28

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  Andrew Metz ,  Yun Han ,  Minjoon Park ,  Ya-Ming Chen

IPC: H01L21/02 ,  H10B43/20

CPC classification number: H01L21/02115 ,  H01L21/02172 ,  H01L21/02488 ,  H01L21/02592 ,  H10B43/20

Abstract: A semiconductor device structure includes a dielectric layer formed on a silicon substrate, an amorphous carbon layer (ACL) formed on the dielectric layer, and a charge dissipation layer formed between the ACL and the dielectric layer. The charge dissipation layer is formed from a material having a resistivity lower than the resistivity of the ACL. Methodologies to fabricate the semiconductor device structure are also disclosed and include forming the dielectric layer on the silicon substrate, forming the charge dissipation layer on the dielectric layer, and forming the ACL on the charge dissipation layer. Alternative semiconductor device structures and fabrication methodologies are also disclosed.

公开(公告)号：US20240234158A1

公开(公告)日：2024-07-11

申请号：US18151223

申请日：2023-01-06

Applicant: Tokyo Electron Limited

Inventor： Indroneil Roy ,  Jason Marion ,  Yusuke Yoshida ,  Yun Han ,  Aelan Mosden ,  Ken Kobayashi

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/30655 ,  H01J37/32816 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31144 ,  H01J2237/3345 ,  H01J2237/3347

Abstract: A method for fabricating a semiconductor device includes forming a pattern of trenches by etching a first layer formed over an underlying layer of a substrate, each of the trenches having an aspect ratio (AR) in a range with a lower limit of a first AR and an upper limit of a second AR, the pattern including a low-AR trench having the first AR and a high-AR trench having the second AR, the AR of a trench being a ratio of its depth to its opening width, the etching including: executing a first recipe in a plasma chamber to anisotropically etch the first layer for a first duration by flowing etchants through the chamber, an etch rate of the first layer being higher on the low-AR trench relative to that on the high-AR trench; and after executing the first recipe, executing a second recipe in the plasma chamber to etch the first layer anisotropically and concurrently deposit oxygen-containing etch byproducts to passivate exposed portions of sides of the trenches, the etch rate of the first layer being lower on the low-AR trench relative to that on the high-AR trench, wherein executing the second recipe increases a relative oxygen content in the plasma chamber from a first value during the executing of the first recipe to a second value.

公开(公告)号：US20240087891A1

公开(公告)日：2024-03-14

申请号：US17931838

申请日：2022-09-13

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Shihsheng Chang ,  Kai-Hung Yu ,  Yun Han

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76802

Abstract: A method of patterning a substrate includes forming a first line, a second line, and a third line over the substrate, the first line, the second line, and the third line being parallel in a plan view, and forming a fourth line and a fifth line over the first line, the second line, and the third line, the fourth line and the fifth line being orthogonal to the first line in the plan view. The method further includes etching a hole through the second line using the first line, the third line, the fourth line, and the fifth line as an etching mask, and filling the hole with a dielectric material to form a block.

公开(公告)号：US11527413B2

公开(公告)日：2022-12-13

申请号：US17162623

申请日：2021-01-29

Applicant: Tokyo Electron Limited

Inventor： Yun Han ,  Peter Ventzek ,  Alok Ranjan

IPC: H01L21/311 ,  H01J37/32

Abstract: A method for processing a substrate includes performing a cyclic plasma etch process including a plurality of cycles, where each cycle of the plurality of cycles includes: causing chemical reactions with the surface of the substrate by exposing a surface of the substrate to fluorine radicals extracted from a first gas discharge plasma formed using a first gaseous mixture including a non-polymerizing fluorine compound; cooling the substrate and concurrently removing residual gaseous byproducts by flowing a second gaseous mixture over the substrate, and at the same time, suppressing the chemical reactions with the surface of the substrate; and performing a plasma surface modification process by exposing the surface of the substrate to hydrogen radicals extracted from a second gas discharge plasma formed using a third gaseous mixture including gases including nitrogen and hydrogen.

公开(公告)号：US20220246438A1

公开(公告)日：2022-08-04

申请号：US17162623

申请日：2021-01-29

Applicant: Tokyo Electron Limited

Inventor： Yun Han ,  Peter Ventzek ,  Alok Ranjan

IPC: H01L21/311 ,  H01J37/32

Abstract: A method for processing a substrate includes performing a cyclic plasma etch process including a plurality of cycles, where each cycle of the plurality of cycles includes: causing chemical reactions with the surface of the substrate by exposing a surface of the substrate to fluorine radicals extracted from a first gas discharge plasma formed using a first gaseous mixture including a non-polymerizing fluorine compound; cooling the substrate and concurrently removing residual gaseous byproducts by flowing a second gaseous mixture over the substrate, and at the same time, suppressing the chemical reactions with the surface of the substrate; and performing a plasma surface modification process by exposing the surface of the substrate to hydrogen radicals extracted from a second gas discharge plasma formed using a third gaseous mixture including gases including nitrogen and hydrogen.

公开(公告)号：US11942307B2

公开(公告)日：2024-03-26

申请号：US17451094

申请日：2021-10-15

Applicant: Tokyo Electron Limited

Inventor： Zhiying Chen ,  Barton Lane ,  Yun Han ,  Peter Lowell George Ventzek ,  Alok Ranjan

IPC: H01J37/32

CPC classification number: H01J37/32174 ,  H01J2237/3341

Abstract: A method for plasma processing includes: sustaining a plasma in a plasma processing chamber, the plasma processing chamber including a first radio frequency (RF) electrode and a second RF electrode, where sustaining the plasma includes: coupling an RF source signal to the first RF electrode; and coupling a bias signal between the first RF electrode and the second RF electrode, the bias signal having a bipolar DC (B-DC) waveform including a plurality of B-DC pulses, each of the B-DC pulses including: a negative bias duration during which the pulse has negative polarity relative to a reference potential, a positive bias duration during which the pulse has positive polarity relative to the reference potential, and a neutral bias duration during which the pulse has neutral polarity relative to the reference potential.

公开(公告)号：US20230317462A1

公开(公告)日：2023-10-05

申请号：US17690715

申请日：2022-03-09

Applicant: Tokyo Electron Limited

Inventor： Yun Han ,  Alok Ranjan ,  Tomoyuki Oishi ,  Shuhei Ogawa ,  Ken Kobayashi ,  Peter Biolsi

IPC: H01L21/3065 ,  H01L21/8234

CPC classification number: H01L21/3065 ,  H01L21/823431

Abstract: A method of processing a substrate that includes: performing a cyclic plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching a patterning layer including a polycrystalline semiconductor material to form or extend a recess by exposing the substrate to a first plasma, the substrate including an oxide layer, the patterning layer formed over the oxide layer, exposing the substrate to a second plasma, the second plasma including dihydrogen, and extending the recess by exposing the substrate to a third plasma, the second plasma being different from the first plasma and the third plasma.

公开(公告)号：US20220301930A1

公开(公告)日：2022-09-22

申请号：US17688343

申请日：2022-03-07

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Shihsheng Chang ,  Ying Trickett ,  Eric Chih-Fang Liu ,  Yun Han ,  Henan Zhang ,  Cory Wajda ,  Robert D. Clark ,  Gerrit J. Leusink ,  Gyanaranjan Pattanaik ,  Hiroaki Niimi

IPC: H01L21/768

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.