公开(公告)号：US20230343592A1

公开(公告)日：2023-10-26

申请号：US17660111

申请日：2022-04-21

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  Andrew Metz ,  Yun Han ,  Ya-Ming Chen ,  Kai-Hung Yu ,  Eric Chih-Fang Liu

IPC: H01L21/033

CPC classification number: H01L21/0332

Abstract: A method of fabricating an amorphous carbon layer (ACL) mask includes forming an ACL on an underlying layer. The ACL includes a soft ACL portion that has a first hardness and a hard ACL portion that has a second hardness. The soft ACL portion underlies the hard ACL portion. The second hardness is greater than the first hardness. The method further includes forming a patterned layer over the ACL and forming an ACL mask by etching through both the soft ACL portion and the hard ACL portion of the ACL to expose the underlying layer using the patterned layer as an etch mask. Forming the ACL may include depositing one or both of the soft ACL portion and the hard ACL portion. Processing conditions may also be varied while forming the ACL to create a hardness gradient that transitions from softer to harder.

公开(公告)号：US11756790B2

公开(公告)日：2023-09-12

申请号：US17196385

申请日：2021-03-09

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Xinghua Sun ,  Shihsheng Chang ,  Eric Chih-Fang Liu ,  Angelique Raley ,  Katie Lutker-Lee

IPC: H01L21/033 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/0332 ,  H01L21/3065 ,  H01L21/3081

Abstract: A method is described for patterning a dielectric layer disposed over a semiconductor substrate layer. The patterning process includes forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer exposing a portion of a major surface of the dielectric layer. A portion of the dielectric layer is removed by a cyclic etch process, where performing one cycle of the cyclic etch process comprises forming a capping layer selectively over the patterned hard mask layer and performing a timed etch process that removes material from the dielectric layer. In another method, the deposition over the hard mask and the removal of the portion of the dielectric layer are performed concurrently.

公开(公告)号：US20220189781A1

公开(公告)日：2022-06-16

申请号：US17514233

申请日：2021-10-29

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  David O'Meara ,  Andrew Metz ,  Yun Han

IPC: H01L21/3065 ,  H01J37/305 ,  H01L21/02 ,  H01J37/32 ,  H01L21/033

Abstract: Improved process flows and methods are provided herein for forming a passivation layer on sidewall surfaces of openings formed in an amorphous carbon layer (ACL) to avoid bowing during an ACL etch process. More specifically, improved process flows and methods are provided to form a silicon-containing passivation layer on sidewall surfaces of the openings created within the ACL without utilizing atomic layer deposition (ALD) techniques or converting the silicon-containing passivation layer to an oxide or a nitride. As such, the improved process flows and methods disclosed herein may be used to protect the sidewall surfaces of the ACL and prevent bowing during the ACL etch process, while also reducing processing time and improving throughput.

公开(公告)号：US12266534B2

公开(公告)日：2025-04-01

申请号：US17316214

申请日：2021-05-10

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  Andrew Metz

IPC: H01L21/308

Abstract: In certain embodiments, a method of forming a semiconductor device includes receiving a substrate having an etch mask layer that includes features for preserving corresponding portions of an underlying hard mask layer to be etched during an etching process. The method includes patterning the hard mask layer using the etch mask layer to gradually form a recess in the hard mask layer, the recess having a depth greater than a width of a top surface of a first feature of the etch mask layer, by performing the etching process. The etching process includes alternating between: depositing, using a first plasma, a silicon-containing protective layer over the etch mask layer and the hard mask layer such that the protective layer covers exposed surfaces of the hard mask layer; and subsequently etching, using a second plasma that comprises oxygen, the hard mask layer to form an incremental portion of the recess.

公开(公告)号：US12237216B2

公开(公告)日：2025-02-25

申请号：US17688343

申请日：2022-03-07

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Shihsheng Chang ,  Ying Trickett ,  Eric Chih-Fang Liu ,  Yun Han ,  Henan Zhang ,  Cory Wajda ,  Robert D. Clark ,  Gerrit J. Leusink ,  Gyanaranjan Pattanaik ,  Hiroaki Niimi

IPC: H01L21/768

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

公开(公告)号：US20240420965A1

公开(公告)日：2024-12-19

申请号：US18337281

申请日：2023-06-19

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  Yen-Tien Lu ,  Du Zhang ,  David L. O'Meara ,  Jeffrey Shearer

IPC: H01L21/311 ,  C23C16/30 ,  C23C16/44 ,  C23C16/455 ,  H01L21/3065

Abstract: A method for processing a substrate that includes: patterning a carbon-based hardmask layer over a dielectric layer to form a first recess in the carbon-based hardmask layer, the first recess having a tapered profile such that a width of the first recess at a first height is greater than a width of the first recess at a second height that is lower than the first height; depositing a metal-containing layer over the patterned carbon-based hardmask layer, the metal-containing layer being physically in contact with sidewalls of the patterned carbon-based hardmask layer in the first recess, the metal-containing layer being thicker at the first height than at the second height; and etching the dielectric layer using the patterned carbon-based hardmask layer as an etch mask by an anisotropic plasma etch process to form a second recess in the dielectric layer.

公开(公告)号：US11538692B2

公开(公告)日：2022-12-27

申请号：US17327305

申请日：2021-05-21

Applicant: Tokyo Electron Limited

Inventor： Yunho Kim ,  Du Zhang ,  Shihsheng Chang ,  Mingmei Wang ,  Andrew Metz

IPC: H01L21/311 ,  H01J37/32

Abstract: A method for processing a substrate includes performing a cyclic process including a plurality of cycles, where the cyclic process includes: forming, in a plasma processing chamber, a passivation layer over sidewalls of a recess in a carbon-containing layer, by exposing the substrate to a first gas including boron, silicon, or aluminum, the carbon-containing layer being disposed over a substrate, purging the plasma processing chamber with a second gas including a hydrogen-containing gas, an oxygen-containing gas, or molecular nitrogen, and exposing the substrate to a plasma generated from the second gas, where each cycle of the plurality of cycles extends the recess vertically into the carbon-containing layer.

公开(公告)号：US11227774B2

公开(公告)日：2022-01-18

申请号：US17104611

申请日：2020-11-25

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  Andrew Metz

IPC: H01L21/311 ,  C23C16/455 ,  H01L21/3065 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3213

Abstract: Methods and systems for etching SiCN with mutli-color selectivity may include receiving the substrate having a multi-line layer formed thereon, the multi-line layer including a region having a pattern of alternating lines of a plurality of materials, wherein each line has a horizontal thickness, a vertical height, and extends horizontally across an underlying layer, wherein each line of the pattern of alternating lines extends vertically from a top surface of the multi-line layer to a bottom surface of the multi-line layer. Such a method may also include forming a patterned recess in the multi-line layer to expose at least a first component of the multi-line layer and a second component of the multi-line layer. An embodiment of a method many also include etching the first component with a non-corrosive etch process that is selective to the second component.

公开(公告)号：US20240371655A1

公开(公告)日：2024-11-07

申请号：US18312427

申请日：2023-05-04

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Shihsheng Chang ,  Nicholas Joy

IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L21/56

Abstract: A method of processing a substrate that includes: forming a patterned hardmask layer over a conductive layer to be etched, the conductive layer disposed over a substrate; and patterning the conductive layer using the patterned hardmask layer as an etch mask, by performing a cyclic plasma etch process to gradually form a recess in the conductive layer, each cycle of the cyclic plasma etch process including exposing the substrate to a first plasma including a halogen to etch the conductive layer, and exposing the substrate to a second plasma including a silicon-containing precursor to deposit a silicon-containing protective layer over a top surface of the patterned hardmask layer.

公开(公告)号：US12040176B2

公开(公告)日：2024-07-16

申请号：US17706408

申请日：2022-03-28

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  Andrew Metz ,  Yun Han ,  Minjoon Park ,  Ya-Ming Chen

IPC: H01L21/02 ,  H10B43/20

CPC classification number: H01L21/02115 ,  H01L21/02172 ,  H01L21/02488 ,  H01L21/02592 ,  H10B43/20

Abstract: A semiconductor device structure includes a dielectric layer formed on a silicon substrate, an amorphous carbon layer (ACL) formed on the dielectric layer, and a charge dissipation layer formed between the ACL and the dielectric layer. The charge dissipation layer is formed from a material having a resistivity lower than the resistivity of the ACL. Methodologies to fabricate the semiconductor device structure are also disclosed and include forming the dielectric layer on the silicon substrate, forming the charge dissipation layer on the dielectric layer, and forming the ACL on the charge dissipation layer. Alternative semiconductor device structures and fabrication methodologies are also disclosed.