公开(公告)号：US11646349B2

公开(公告)日：2023-05-09

申请号：US17511579

申请日：2021-10-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Hsu ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Tsai-Yu Wen ,  Shi You Liu ,  Yu-Hsiang Lin

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/167 ,  H01L29/06

CPC classification number: H01L29/105 ,  H01L21/26506 ,  H01L29/0649 ,  H01L29/167

Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.

公开(公告)号：US11600531B2

公开(公告)日：2023-03-07

申请号：US17338696

申请日：2021-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, and a metal gate adjacent to the isolation structure. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

公开(公告)号：US20220093798A1

公开(公告)日：2022-03-24

申请号：US17073038

申请日：2020-10-16

Applicant: United Microelectronics Corp.

Inventor： Chun-Ya Chiu ,  Chih-Kai Hsu ,  Chin-Hung Chen ,  Chia-Jung Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L21/02

Abstract: The disclosure discloses a structure of high-voltage (HV) transistor which includes a substrate. An epitaxial doped structure with a first conductive type is formed in the substrate, wherein a top portion of the epitaxial doped structure includes a top undoped epitaxial layer. A gate structure is disposed on the substrate and at least overlapping with the top undoped epitaxial layer. A source/drain (S/D) region with a second conductive type is formed in the epitaxial doped structure at a side of the gate structure. The first conductive type is different from the second conductive type.

公开(公告)号：US20220093411A1

公开(公告)日：2022-03-24

申请号：US17030158

申请日：2020-09-23

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Hsu ,  Chun Yu Chen ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin

IPC: H01L21/324 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311

Abstract: A method for fabricating a high-voltage (HV) transistor is provided. The method includes providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures. Further, a hydrogen annealing process is performed over the recess. A sacrificial dielectric layer is formed on the recess. The sacrificial dielectric layer is removed, wherein a portion of the first and second isolation structures is also removed. A gate oxide layer is formed in the recess between the first and second isolation structures after the hydrogen annealing process.

公开(公告)号：US11195918B1

公开(公告)日：2021-12-07

申请号：US17026062

申请日：2020-09-18

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Hsu ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Tsai-Yu Wen ,  Shi You Liu ,  Yu-Hsiang Lin

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/167 ,  H01L29/06

Abstract: A structure of semiconductor device is provided, including a substrate. A first trench isolation and a second trench isolation are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the germanium doped layer region.

公开(公告)号：US20210104554A1

公开(公告)日：2021-04-08

申请号：US16699474

申请日：2019-11-29

Applicant: United Microelectronics Corp.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Chung-Liang Chu ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.

公开(公告)号：US10971397B2

公开(公告)日：2021-04-06

申请号：US16569544

申请日：2019-09-12

Applicant: United Microelectronics Corp.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chia-Jung Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/768 ,  H01L27/108

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.

公开(公告)号：US20210050456A1

公开(公告)日：2021-02-18

申请号：US16572556

申请日：2019-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.

公开(公告)号：US10818556B2

公开(公告)日：2020-10-27

申请号：US16223036

申请日：2018-12-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Yeh Liu ,  Jia-Feng Fang ,  Yu-Hsiang Lin ,  Ching-Hsiang Chiu ,  Chia-Wei Liu

IPC: H01L29/00 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/027

Abstract: A method for forming a semiconductor structure is provided. Multiple fins extending along a first direction are formed in a semiconductor substrate. The multiple fins includes a group of active fins, a pair of protection fins sandwiching about the group the active fins, and at least one dummy fin around the pair of protection fins. A fin cut process is performed to remove the at least one dummy fin around the pair of protection fins. After performing the fin cut process, trench isolation structures are formed within the trenches between the multiple fins. The trench isolation structures are subjected to an anneal process. After annealing the trench isolation structures, the pair of protection fins is removed.

公开(公告)号：US10658241B2

公开(公告)日：2020-05-19

申请号：US15839769

申请日：2017-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

IPC: H01L21/82 ,  H01L27/02 ,  H01L27/088 ,  H01L23/522 ,  H01L23/528 ,  H01L23/50 ,  H01L27/092 ,  H01L29/78

Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern, wherein the first pattern includes a first feature and a first jog part protruding from and orthogonal to the first feature. A second reticle is used to form a second pattern, wherein the second pattern includes a second feature, and the first feature is between the second feature and the first jog part. A third reticle is used to form a third pattern, wherein the third pattern includes a third-one feature overlapping the first jog part and a third-two feature overlapping the second feature.