公开(公告)号：US09679898B2

公开(公告)日：2017-06-13

申请号：US15339945

申请日：2016-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Ya-Huei Tsai

IPC: H01L21/00 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/82345 ,  H01L21/8238 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device having metal gate includes a first metal gate structure and a second metal gate structure disposed in a first device region and in a second device region on a substrate respectively. The first metal gate structure includes a gate insulating layer, a first bottom barrier layer, a top barrier layer, and a metal layer disposed on the substrate in order, wherein the top barrier layer is directly in contact with the first bottom barrier layer. The second metal gate structure includes the gate insulating layer, a second bottom barrier layer, the top barrier layer, and the metal layer on the substrate in order, wherein the top barrier layer is directly in contact with the second bottom barrier layer. The first bottom barrier layer and the second bottom barrier layer have different impurity compositions.

公开(公告)号：US09524967B1

公开(公告)日：2016-12-20

申请号：US15046458

申请日：2016-02-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Yeh Liu ,  Chien-Ming Lai ,  Yu-Ping Wang ,  Mon-Sen Lin ,  Ya-Huei Tsai ,  Ching-Hsiang Chiu

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092

Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first transistor, a second transistor and a third transistor all disposed on the substrate. The first transistor includes a first channel, and a first barrier layer and a first work function layer stacked with each other on the first channel. The second transistor includes a second channel, and a second barrier layer and a second work function layer stacked with each other. The third transistor includes a third channel and a third barrier layer and a third work function layer stacked with each other on the third channel, wherein the first barrier layer, the second barrier layer and the third barrier layer have different nitrogen ratio. The first, the second and the third transistors have different threshold voltages, respectively.

Abstract translation: 半导体器件及其形成方法，所述半导体器件包括基板，以及全部设置在所述基板上的第一晶体管，第二晶体管和第三晶体管。 第一晶体管包括第一通道，以及在第一通道上彼此堆叠的第一势垒层和第一功函数层。 第二晶体管包括第二通道，以及彼此堆叠的第二阻挡层和第二功能层。 第三晶体管包括在第三沟道上彼此堆叠的第三沟道和第三势垒层和第三功函数层，其中第一势垒层，第二阻挡层和第三势垒层具有不同的氮比。 第一，第二和第三晶体管分别具有不同的阈值电压。

公开(公告)号：US09412743B2

公开(公告)日：2016-08-09

申请号：US14526552

申请日：2014-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Chien-Chung Huang ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/3211 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种互补金属氧化物半导体器件，其包括PMOS和NMOS。 PMOS具有P型金属栅极，其包括底部阻挡层，P功函数金属（PWFM）层，N功函数调整（NWFT）层，N功函数金属（NWFM）层和金属层。 NMOS具有N型金属栅极，其包括NWFT层，NWFM层和低电阻层。 本发明还提供一种形成该方法的方法。

公开(公告)号：US09349822B2

公开(公告)日：2016-05-24

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L27/092

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US20160035854A1

公开(公告)日：2016-02-04

申请号：US14881162

申请日：2015-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有NMOS区和PMOS区的衬底; 在NMOS区域和PMOS区域分别形成虚拟栅极; 从所述NMOS区域和所述PMOS区域中的每一个去除所述伪栅极; 在NMOS区域和PMOS区域上形成n型功函数层; 去除PMOS区域中的n型功函数层; 在NMOS区域和PMOS区域上形成p型功函数层; 以及在NMOS区域和PMOS区域的p型功函数层上沉积低电阻金属层。

公开(公告)号：US20150332976A1

公开(公告)日：2015-11-19

申请号：US14811814

申请日：2015-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Chien-Ting Lin ,  Chien-Ming Lai ,  Chi-Mao Hsu

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/321 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32115 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L29/7833

Abstract: A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括以下步骤。 提供了具有形成在其上的第一半导体器件和第二半导体器件的衬底。 第一半导体器件包括第一栅极沟槽，第二半导体器件包括第二栅极沟槽。 在第一栅极沟槽和第二栅极沟槽中形成第一功函数金属层。 第一功函数金属层的一部分从第二栅极沟槽去除。 在第一栅极沟槽和第二栅极沟槽中形成第二功函数金属层。 第二功函数金属层和第一功函数金属层包括相同的金属材料。 在第一栅极沟槽和第二栅极沟槽中依次形成第三功函数金属层和间隙填充金属层。

公开(公告)号：US20150243754A1

公开(公告)日：2015-08-27

申请号：US14187701

申请日：2014-02-24

Applicant: United Microelectronics Corp.

Inventor： Hung-Yi Wu ,  Chien-Ming Lai ,  Yi-Wen Chen

IPC: H01L29/49 ,  H01L29/40

CPC classification number: H01L29/4966 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.

Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括隔离层，栅介质层，第一功函数金属，第一底阻挡层，第二功函数金属和第一顶阻挡层。 隔离层形成在衬底上并具有第一栅极沟槽。 栅介质层形成在第一栅极沟槽中。 第一功函数金属形成在第一栅极沟槽中的栅介质层上。 第一底部阻挡层形成在第一功函数金属上。 第二功能金属形成在第一底部阻挡层上。 第一顶部阻挡层形成在第二功函数金属上。

公开(公告)号：US20140339652A1

公开(公告)日：2014-11-20

申请号：US14449157

申请日：2014-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

IPC: H01L29/51 ,  H01L29/49

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846

Abstract: A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer.

Abstract translation: 具有含氧金属栅极的半导体器件包括衬底，栅介质层和多层堆叠结构。 多层堆叠结构设置在基板上。 多层堆叠结构的至少一层包括功函数金属层。 更靠近栅介质层的多层堆叠结构的一层侧的氧的浓度小于与栅介质层相反的多层堆叠结构的一层的一侧的浓度。

公开(公告)号：US20240120303A1

公开(公告)日：2024-04-11

申请号：US17980568

申请日：2022-11-04

Applicant: United Microelectronics Corp.

Inventor： Chien-Ming Lai

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/08 ,  H01L23/49822 ,  H01L2224/08111 ,  H01L2224/08147

Abstract: A semiconductor structure including a first substrate, a first conductive layer, and first bonding pads is provided. The first conductive layer is located on the first substrate. The first conductive layer includes a main body portion and an extension portion. The extension portion is connected to the main body portion and includes a terminal portion away from the main body portion. The first bonding pads are connected to the main body portion and the extension portion. The number of the first bonding pads connected to the terminal portion of the extension portion is plural.

公开(公告)号：US11631771B2

公开(公告)日：2023-04-18

申请号：US17367637

申请日：2021-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Yen-Chen Chen ,  Jen-Po Huang ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Qinggang Xing ,  Ding-Lung Chen ,  Li Li Ding ,  Yao-Hung Liu

IPC: H01L29/76 ,  H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.