公开(公告)号：US08841976B2

公开(公告)日：2014-09-23

申请号：US13345974

申请日：2012-01-09

Applicant: Taiji Ogawa ,  Hirohito Watanabe ,  Masazaku Sato

Inventor： Taiji Ogawa ,  Hirohito Watanabe ,  Masazaku Sato

IPC: H01P3/08 ,  H05K1/02

CPC classification number: H05K1/024 ,  H01P3/081 ,  H05K1/0225 ,  H05K1/0245 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/09681

Abstract: The printed wiring board has a conductor of signal line 41 and two conductive lines 42 on one face of the first insulating layer 10 covered by a second insulating layer 20, while having a ground layer of the ground 30 potential on the opposite face thereof, when the dielectric tangent A of the second insulating layer (insulating layer A) 20 is larger than the dielectric tangent B of the first insulating layer (insulating layer B) 10, Relational Expression 1: (relative permittivity B)·(width (W41) of signal line(s) 41)/(thickness (T10) of first insulating layer (insulating layer B) 10)>(relative permittivity A)·{(thickness (T41) of signal line(s) 41)/(distance (S1) between signal line(s) 41 and one conductive line 42a)+(thickness (T41) of signal line(s) 41)/(distance (S2) between signal line(s) 41 and other conductive line 42b)+(thickness (T41) of signal lines 41)/(distance (S3) between pair of signal lines (41a and 41b)·2} is satisfied.

Abstract translation: 印刷电路板具有由第二绝缘层20覆盖的第一绝缘层10的一面上的信号线41的导体和两条导线42，同时在其相对面上具有接地层30的电位的地层， 第二绝缘层（绝缘层A）20的介质切线A大于第一绝缘层（绝缘层B）10的介质切线B，关系式1（相对介电常数B）·（宽（W41） 信号线41）/（第一绝缘层（绝缘层B）的厚度（T10））10）>（相对介电常数A）·{（信号线的厚度（T41）41）/（距离（S1 信号线41和一根导线42a之间）+（信号线41的厚度（T41））/（信号线41与其他导线42b的距离（S2））+（厚度 信号线41的（T41）/（信号线对（41a，41b）·2之间的距离（S3））满足。

公开(公告)号：US08816711B2

公开(公告)日：2014-08-26

申请号：US12547561

申请日：2009-08-26

Applicant: David R. Lyders ,  George Alan Salisbury

Inventor： David R. Lyders ,  George Alan Salisbury

IPC: G01R1/067 ,  H01Q1/36 ,  H01J49/40 ,  H05K1/11 ,  H01R24/58 ,  H01R107/00 ,  H05K1/14

CPC classification number: H05K1/118 ,  H01R24/58 ,  H01R2107/00 ,  H05K1/147 ,  H05K2201/055 ,  H05K2201/056 ,  H05K2201/09236 ,  Y10T29/532

Abstract: An electrical probe assembly includes a flexible circuit. A plurality of electrically conductive regions is on a first side of the flexible circuit. The flexible circuit is arranged about an axis formed by rolling the flexible circuit such that the electrically conductive regions form a plurality of isolated electrically conductive bands.

Abstract translation: 电探头组件包括柔性电路。 多个导电区域在柔性电路的第一侧上。 柔性电路围绕通过滚动柔性电路形成的轴线布置，使得导电区域形成多个隔离的导电带。

公开(公告)号：US20140209367A1

公开(公告)日：2014-07-31

申请号：US14342019

申请日：2012-09-06

Applicant: Jun Sakai ,  Koichiro Nakase

Inventor： Jun Sakai ,  Koichiro Nakase

IPC: H05K1/02

CPC classification number: H05K1/0233 ,  H01P1/20 ,  H01P3/088 ,  H01P5/028 ,  H05K1/0225 ,  H05K1/0227 ,  H05K1/0239 ,  H05K1/165 ,  H05K2201/09236 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/1003

Abstract: It is impossible to make a wiring board for noise suppression thinner, therefore, a wiring board according to an exemplary aspect of the invention includes a first wiring layer, an intermediate layer, and a second wiring layer; wherein the second wiring layer, the intermediate layer, and the first wiring layer are stacked in this order; the first wiring layer comprises a first wiring and a second wiring separated from the first wiring; the intermediate layer comprises a first via and a second via; the second wiring layer comprises a third wiring and a non-wiring portion where wirings are not formed; the first wiring is separated from the third wiring; the first via and the second via electrically connect the second wiring to the third wiring respectively; the non-wiring portion is located at a portion corresponding to an area between the first via and the second via; and the first wiring and the second wiring cross over the non-wiring portion.

Abstract translation: 因此，根据本发明的一个实施方式的布线基板，具有第一布线层，中间层和第二布线层，不可能使噪声抑制用布线板变薄。 其中所述第二布线层，所述中间层和所述第一布线层以该顺序堆叠; 第一布线层包括与第一布线分离的第一布线和第二布线; 中间层包括第一通孔和第二通孔; 第二布线层包括第三布线和不形成布线的非布线部分; 第一布线与第三布线分离; 第一通孔和第二通孔分别将第二布线电连接到第三布线; 非布线部分位于与第一通孔和第二通孔之间的区域相对应的部分; 并且第一布线和第二布线跨越非布线部分。

公开(公告)号：US08779874B2

公开(公告)日：2014-07-15

申请号：US12457801

申请日：2009-06-22

Applicant: Hiroshi Toyao

Inventor： Hiroshi Toyao

IPC: H01P1/20

CPC classification number: H01P3/026 ,  H01P1/2005 ,  H01P1/2013 ,  H01P3/006 ,  H01P3/081 ,  H01P5/028 ,  H01P7/082 ,  H01Q9/04 ,  H05K1/0236 ,  H05K1/165 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09309

Abstract: A waveguide structure or a printed-circuit board is formed using a plurality of unit structures which are repetitively aligned in a one-dimensional manner or in a two-dimensional manner. The unit structure includes first and second conductive planes which are disposed in parallel with each other, a transmission line having an open end which is formed in a layer different from the first and second conductive planes and positioned to face the second conductive plane, and a conductive via electrically connecting the transmission line to the first conductive plane.

Abstract translation: 使用以一维方式或二维方式重复对准的多个单位结构形成波导结构或印刷电路板。 单元结构包括彼此平行设置的第一和第二导电平面，具有开口端的传输线，该开口端形成在与第一和第二导电平面不同的位置并且定位成面对第二导电平面，并且 通过将传输线电连接到第一导电平面而导电。

公开(公告)号：US08760238B2

公开(公告)日：2014-06-24

申请号：US13726259

申请日：2012-12-24

Applicant: Hon Hai Precision Industry Co., Ltd.

Inventor： Chien-Hsun Chen ,  Po-Chuan Hsieh

IPC: H04B3/14

CPC classification number: H04B3/14 ,  H05K1/0222 ,  H05K1/0234 ,  H05K1/0245 ,  H05K1/025 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/10022

Abstract: An equalizer for compensating transmission losses of electronic communication signals includes a circuit board and a compensation module. The compensation module includes a pair of input pins, a pair of output pins, first and second resistors, first and second vias, and a pair of micro-strips. When a signal transmitted by the circuit board is received by the input pins, a first part of the signal is directly outputted from the output pins, a second part of the signal is reflected by the first resistor and transmitted back to the output pins to be outputted, and a third part of the signal is reflected by the second resistor and transmitted back to the output pins to be outputted, such that the output of the equalizer applies two stages of compensation.

Abstract translation: 用于补偿电子通信信号的传输损耗的均衡器包括电路板和补偿模块。 补偿模块包括一对输入引脚，一对输出引脚，第一和第二电阻器，第一和第二通孔以及一对微带。 当由输入引脚接收到由电路板发送的信号时，信号的第一部分从输出引脚直接输出，信号的第二部分被第一电阻反射并传输回输出引脚 输出，信号的第三部分被第二电阻反射并被发送回输出引脚以输出，使得均衡器的输出施加两级补偿。

公开(公告)号：US20140160826A1

公开(公告)日：2014-06-12

申请号：US14182821

申请日：2014-02-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi BETSUI ,  Naoto TAOKA ,  Motoo SUWA ,  Shigezumi MATSUI ,  Norihiko SUGITA ,  Yoshiharu FUKUSHIMA

IPC: G11C5/02

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract translation: 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下，与仅在一侧具有存储器接口电路的半导体板相比，可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此，微型计算机在主板和模块板上简化了线路设计。

公开(公告)号：US08715013B2

公开(公告)日：2014-05-06

申请号：US13549024

申请日：2012-07-13

Applicant: Jack E. Caveney ,  Scott M. Lesniak

Inventor： Jack E. Caveney ,  Scott M. Lesniak

IPC: H01R24/00

CPC classification number: H01R4/2416 ,  H01R4/2433 ,  H01R13/6466 ,  H01R13/6469 ,  H01R13/665 ,  H01R13/6658 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10S439/942 ,  Y10T29/49201 ,  Y10T29/49202 ,  Y10T29/49204 ,  Y10T29/49208

Abstract: A network cable jack includes a printed circuit board (PCB) for balancing both inductive and capacitive coupling. Using a PCB allows compact trace paths to be formed without significantly increasing manufacturing costs. By including on each trace path two distinct inductance zones separated by a neutral zone, significant gains in degrees of freedom are achieved for designing PCB trace patterns in which a pair of inductive coupling zones jointly offset the inductive coupling caused by a specification plug and the jack contacts, both in magnitude and phase angle. Further, using distinct inductance zones offers more freedom regarding the placement of capacitive plates for use in capacitance balancing as well as the placement of terminals and insulation displacement contacts. Although the magnitude of a capacitive coupling is determined by the length of the capacitor plates parallel to current carrying traces, the approach allows capacitive and inductive coupling to be balanced independently.

Abstract translation: 网络电缆插孔包括用于平衡电感和电容耦合的印刷电路板（PCB）。 使用PCB可以形成紧凑的轨迹路径，而不会显着增加制造成本。 通过在每个迹线路径上包括两个由中性区域分开的不同的电感区域，实现了自由度的显着增益，用于设计PCB迹线图案，其中一对感应耦合区域共同抵消了由规格插头和插孔引起的感性耦合 触点，幅度和相位角。 此外，使用不同的电感区域可以提供更多的自由度，用于电容平板的放置以及端子和绝缘位移触点的放置。 虽然电容耦合的大小由与载流轨迹平行的电容器板的长度确定，但该方法允许电容和电感耦合独立平衡。

公开(公告)号：US20140123327A1

公开(公告)日：2014-05-01

申请号：US14127821

申请日：2012-03-16

Applicant: Nubuo Takahashi

Inventor： Nubuo Takahashi

IPC: G06F21/82 ,  G01R19/00

CPC classification number: G06F21/86 ,  G01R19/00 ,  G06F21/82 ,  H05K1/0268 ,  H05K1/0275 ,  H05K1/0298 ,  H05K1/118 ,  H05K2201/05 ,  H05K2201/09236

Abstract: It is an object of this invention to provide an FPC capable of improving tamper resistance. An FPC (1) of this invention includes: a signal line pattern (2) for inputting a communication signal; and signal protective line patterns (3, 4) provided to be opposed to an upper surface and a lower surface of the signal line pattern and having the same width as a width of the signal line pattern (2) or a larger width than the width of the signal line pattern (2). The signal protective line patterns are provided along the signal line pattern within a region that requires tamper resistance.

Abstract translation: 本发明的目的是提供一种能够提高防篡改性的FPC。 本发明的FPC（1）包括：用于输入通信信号的信号线图形（2）; 以及设置成与信号线图案的上表面和下表面相对并且具有与信号线图案（2）的宽度相同的宽度或宽度大于宽度的信号保护线图案（3,4） 的信号线图案（2）。 信号保护线图案沿着需要防篡改的区域内的信号线图形提供。

公开(公告)号：US08633394B2

公开(公告)日：2014-01-21

申请号：US12780960

申请日：2010-05-17

Applicant: Ying-Tso Lai ,  Hsiao-Yun Su

Inventor： Ying-Tso Lai ,  Hsiao-Yun Su

IPC: H05K1/00

CPC classification number: H05K1/0253 ,  H05K1/0219 ,  H05K1/0227 ,  H05K1/028 ,  H05K2201/09236 ,  H05K2201/0969

Abstract: A FPCB includes a signal layer, a ground layer, and a dielectric layer lying between the signal layer and the ground layer. At least one high speed signal transmission line is formed on the signal layer. The ground layer has a copper-removed area corresponding to the transmission line. Two ground lines are symmetrically disposed at two opposite sides of the signal transmission line and substantially parallel to the signal transmission line, each ground line and the signal transmission line is spaced at a first predetermined distance. Each ground line and the signal transmission line are spaced at a first predetermined distance.

Abstract translation: FPCB包括位于信号层和接地层之间的信号层，接地层和电介质层。 在信号层上形成至少一条高速信号传输线。 接地层具有对应于传输线的铜去除区域。 两个接地线对称地设置在信号传输线的两个相对侧并且基本上平行于信号传输线，每个接地线和信号传输线以第一预定距离间隔开。 每个接地线和信号传输线以第一预定距离隔开。

公开(公告)号：US08609996B2

公开(公告)日：2013-12-17

申请号：US13715054

申请日：2012-12-14

Applicant: Hon Hai Precision Industry Co., Ltd.

Inventor： Yu-Hsu Lin

IPC: H05K1/11

CPC classification number: H05K1/00 ,  G06F17/5068 ,  H05K1/0245 ,  H05K3/0005 ,  H05K2201/09236 ,  H05K2201/09318

Abstract: A printed circuit board includes a signal layer having a pair of differential transmission lines thereon. An eye width and an eye height of an eye diagram obtained at output terminals of the pair of differential transmission lines are variable according to a distance between the pair of differential transmission lines. The eye width and the eye height of the eye diagram are at minimum values when the distance between the pair of differential transmission lines is at a first distance. The eye width and the eye height meet requirements of the pair of differential transmission lines for the eye diagram when the distance between the pair of differential transmission lines is set at a second distance, the second distance is less than the first distance.

Abstract translation: 印刷电路板包括其上具有一对差动传输线的信号层。 在一对差动传输线的输出端获得的眼图的眼睛宽度和眼睛高度根据一对差动传输线之间的距离而变化。 当一对差动传输线之间的距离处于第一距离时，眼图的眼睛宽度和眼睛高度是最小值。 当一对差动传输线之间的距离设定在第二距离时，眼睛宽度和眼睛高度满足用于眼图的一对差动传输线的要求，第二距离小于第一距离。