公开(公告)号：US20090243649A1

公开(公告)日：2009-10-01

申请号：US12480589

申请日：2009-06-08

Applicant: George E. Pax ,  Roy E. Greeff

Inventor： George E. Pax ,  Roy E. Greeff

IPC: H03K19/003

CPC classification number: G11C5/04 ,  G11C5/025 ,  G11C5/063 ,  G11C11/409 ,  H05K1/025 ,  H05K1/181 ,  H05K2201/09254 ,  Y02P70/611

Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

Abstract translation: 注册的存储器模块包括通过形成对称树形拓扑的多条传输线耦合到寄存器的多个存储器件。 树包括几个分支，每个分支包括仅在其端部耦合到另一个传输线或一个存储器件的两个传输线。 分支被布置成几层次，分支中的传输线具有相同长度的相同层级。 每个传输线优选地具有特性阻抗，其是与其耦合的任何一对下游传输线的特性阻抗的一半以提供阻抗匹配。 专用传输线用于将附加的存储器件（其可能是或可能不是错误检查存储器件）耦合到寄存器。

公开(公告)号：US20090114958A1

公开(公告)日：2009-05-07

申请号：US12264936

申请日：2008-11-05

Applicant: Norio Nakazato ,  Nobuo Fujieda ,  Masayoshi Ishibashi ,  Midori Kato ,  Tadashi Arai ,  Takeo Shiba

Inventor： Norio Nakazato ,  Nobuo Fujieda ,  Masayoshi Ishibashi ,  Midori Kato ,  Tadashi Arai ,  Takeo Shiba

IPC: H01L29/78 ,  H01L21/311

CPC classification number: H01L21/4867 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/09036 ,  H05K2201/09254 ,  H01L2924/00

Abstract: A wiring board with an electronic device comprising a plurality of trenches arranged in parallel on a substrate, a common trench communicating the plurality of trenches with each other at one of their ends on the substrate, a metal layer formed at the bottom of the plurality of trenches, and an electrode layer connected with the metal layer and formed on a bottom of the common trench, wherein the electrode layer on the bottom of the common trench constitutes a source electrode or a drain electrode of a field effect transistor, whereby the wiring board and an electronic circuit having a good fine wire pattern and a good narrow gap between the patterns using a coating material can be formed, and a reduction for a cost of an organic thin film electronic device and the electronic circuit can be attained since they can be realized through a development of a printing technique.

Abstract translation: 一种具有电子装置的布线板，包括平行布置在基板上的多个沟槽，在所述基板的一端的一端将所述多个沟槽彼此连通的公共沟槽，形成在所述多个栅极的底部的金属层 沟槽，和与金属层连接并形成在公共沟槽的底部上的电极层，其中公共沟槽的底部上的电极层构成场效应晶体管的源电极或漏电极，由此布线板 并且可以形成具有良好细线图案和使用涂料的图案之间良好窄间隙的电子电路，并且可以实现有机薄膜电子器件和电子电路的成本降低，因为它们可以是 通过开发印刷技术实现。

公开(公告)号：US20090086522A1

公开(公告)日：2009-04-02

申请号：US12239900

申请日：2008-09-29

Applicant: Atsushi HIRAISHI ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

Inventor： Atsushi HIRAISHI ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

IPC: G11C5/06 ,  H05K1/18 ,  H05K7/00

CPC classification number: G11C5/063 ,  G11C5/04 ,  G11C8/14 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/10159 ,  Y02P70/611

Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

Abstract translation: 具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。 数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。 从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。 从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

公开(公告)号：US20080123303A1

公开(公告)日：2008-05-29

申请号：US11987080

申请日：2007-11-27

Applicant: Toshio Sugano ,  Shunichi Saito ,  Atsushi Hiraishi

Inventor： Toshio Sugano ,  Shunichi Saito ,  Atsushi Hiraishi

IPC: H05K7/00

CPC classification number: H05K1/181 ,  G11C5/00 ,  H05K1/0298 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/10159 ,  H05K2201/10545 ,  Y02P70/611

Abstract: A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.

Abstract translation: 存储器模块包括经由模块基板设置在与存储器缓冲器相对的位置处的存储器芯片MC1，经由模块基板设置在与存储器缓冲器不相对的位置处的存储芯片MC 3和布置在存储器缓冲器 在与存储芯片MC3相对的位置经由模块基板。 连接到存储芯片MC 1的布线部分和连接到存储芯片MC 3和MC 11的布线部分分支的分支点位于从平面安装位置 的存储器缓冲器和存储芯片MC 3和MC 11的平面安装位置。因此，可以使布线部分的布线长度足够短。

公开(公告)号：US07346880B2

公开(公告)日：2008-03-18

申请号：US11171576

申请日：2005-06-30

Applicant: Choupin B. Huang ,  Charles T. Ballou ,  Ramesh K. R. Velugoti ,  Drin-Guang W. Chen

Inventor： Choupin B. Huang ,  Charles T. Ballou ,  Ramesh K. R. Velugoti ,  Drin-Guang W. Chen

IPC: G06F17/50

CPC classification number: G06F1/10 ,  H05K1/023 ,  H05K1/0245 ,  H05K1/0246 ,  H05K1/0248 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2201/10689

Abstract: Methods and arrangements to gang differential clock signals to attenuate pin-to-pin output skew for a clock driver are disclosed. Embodiments may comprise a pattern of conductors to interconnect output pins for differential clock signals with termination resistors. The pattern of conductors comprises a group of conductors for a positive clock (p-clock) signal and a group of conductors for a negative clock (n-clock) signal. The conductors for the p-clock signal intersect at a gang point between the output pins and pads for the termination resistors. Similarly, the conductors for the n-clock signals intersect at a gang point between the pins and the pads. In many embodiments, the distance between the pins and pads may be approximately 120 mils. In further embodiments, the distance may be longer or shorter than 120 mils. Other embodiments are disclosed and claimed.

Abstract translation: 公开了组合差分时钟信号以衰减时钟驱动器的引脚到引脚输出偏移的方法和布置。 实施例可以包括用于将用于差分时钟信号的输出引脚互连到终端电阻器的导体图案。 导体图案包括用于正时钟（p时钟）信号的一组导体和用于负时钟（n时钟）信号的一组导体。 用于p时钟信号的导体在终端电阻的输出引脚和焊盘之间的帮派点处相交。 类似地，n时钟信号的导体在引脚和焊盘之间的帮派点相交。 在许多实施例中，引脚和焊盘之间的距离可以是大约120密耳。 在另外的实施例中，该距离可以长于或短于120密耳。 公开和要求保护其他实施例。

公开(公告)号：US07331794B2

公开(公告)日：2008-02-19

申请号：US11440069

申请日：2006-05-25

Applicant: Nicolas Imbert ,  Charles Chuc

Inventor： Nicolas Imbert ,  Charles Chuc

IPC: H01R12/00

CPC classification number: H05K7/1459 ,  H01R12/52 ,  H01R31/005 ,  H05K1/0289 ,  H05K1/14 ,  H05K1/148 ,  H05K7/1441 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09972

Abstract: A device (20) for interconnecting electrical bundles, includes a plurality of pluggable connection and cross-connect cards (34 to 38) for the electrical bundles. The device further includes a “main” printed circuit (28, 28b) fitted with connectors or slots (29 to 33) designed and arranged to receive the pluggable cards, the printed circuit having a plurality of parallel tracks (46), each enabling two tracks (61 to 63, 68) or tracks starters (70 to 72) provided respectively on two distinct pluggable cards plugged in the connectors of the main printed circuit to be put to the same potential, each of the parallel tracks (46) being in contact with a respective pin (50, 150) of a plurality of connectors of the main printed circuit.

Abstract translation: 用于互连电束的装置（20）包括用于电束的多个可插拔连接和交叉连接卡（34至38）。 该装置还包括装配有设计和布置成接收可插拔卡的连接器或槽（29至33）的“主”印刷电路（28,28b），印刷电路具有多个平行轨道（46），每个启用 两个轨道（61至63,68）或轨道起动器（70至72）分别设置在插入主印刷电路的连接器中以插入相同电位的两个不同的可插拔卡上，每个平行轨道（46）为 与主印刷电路的多个连接器的相应销（50,150）接触。

公开(公告)号：US20080036492A1

公开(公告)日：2008-02-14

申请号：US11973684

申请日：2007-10-09

Applicant: George Pax ,  Roy Greeff

Inventor： George Pax ,  Roy Greeff

IPC: H03K19/003

CPC classification number: G11C5/04 ,  G11C5/025 ,  G11C5/063 ,  G11C11/409 ,  H05K1/025 ,  H05K1/181 ,  H05K2201/09254 ,  Y02P70/611

Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

Abstract translation: 注册的存储器模块包括通过形成对称树形拓扑的多条传输线耦合到寄存器的多个存储器件。 树包括几个分支，每个分支包括仅在其端部耦合到另一个传输线或一个存储器件的两个传输线。 分支被布置成几层次，分支中的传输线具有相同长度的相同层级。 每个传输线优选地具有特性阻抗，其是与其耦合的任何一对下游传输线的特性阻抗的一半以提供阻抗匹配。 专用传输线用于将附加的存储器件（其可能是或可能不是错误检查存储器件）耦合到寄存器。

公开(公告)号：US20080024143A1

公开(公告)日：2008-01-31

申请号：US11866024

申请日：2007-10-02

Applicant: Charles Miller ,  John Long

Inventor： Charles Miller ,  John Long

IPC: H01H31/02

CPC classification number: G01R31/31926 ,  G01R1/07378 ,  G01R31/318511 ,  G11C29/56 ,  G11C2029/2602 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0289 ,  H05K2201/09254 ,  Y10T29/49117

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

Abstract translation: 互连结构采用闭合栅格总线将集成电路测试器通道连接到半导体晶片上的输入/输出（I / O）焊盘阵列，使得测试仪通道可以同时与所有I / O焊盘通信。 互连结构包括实现总线节点阵列的电路板，每个总线节点对应于单独的一个I / O焊盘。 电路板包括至少两层。 安装在第一层上的轨迹形成一组第一个菊花链总线，每个链路总线连接总线节点阵列的单独行的所有总线节点。 安装在第二电路板层上的迹线形成一组第二菊花链总线，每条链路总线连接总线节点阵列的单独列的所有总线节点。 第一和第二菊花链总线的通路和其他电路板互连端，使得它们形成闭合栅格总线。 每个总线节点通过单独的隔离电阻器连接到安装在电路板表面上的单独的接触焊盘。 一组弹簧触点或探针将每个接触垫连接到晶片上的单独的I / O焊盘之间。

公开(公告)号：US07307862B2

公开(公告)日：2007-12-11

申请号：US10655927

申请日：2003-09-04

Applicant: Mike Cogdill ,  Idis Ramona Martinez ,  Derek Steven Schumacher

Inventor： Mike Cogdill ,  Idis Ramona Martinez ,  Derek Steven Schumacher

IPC: G11C5/06

CPC classification number: H05K1/0246 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1066 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2203/1572

Abstract: A circuit and system for improving signal integrity in a memory system. The circuit has a transmission line having a dampening impedance between a driver and a branch point of the transmission line. The circuit also has a termination impedance having one end coupled to the transmission line between the dampening impedance and the branch point. The transmission line has branches coupled to memory module interfaces. The branches have respective lengths between the branch point and the memory module interfaces to be configured symmetrically, wherein the branch point is at a point to balance signal transmission on the branches.

Abstract translation: 一种用于改善存储器系统中的信号完整性的电路和系统。 电路具有在驱动器和传输线的分支点之间具有阻尼阻抗的传输线。 电路还具有端接阻抗，其一端耦合到阻尼阻抗和分支点之间的传输线。 传输线具有耦合到存储器模块接口的分支。 分支在分支点和存储器模块接口之间具有对称配置的相应长度，其中分支点处于平衡分支上的信号传输的点。

公开(公告)号：US20070279881A1

公开(公告)日：2007-12-06

申请号：US11757265

申请日：2007-06-01

Applicant: Steve WEIR ,  Scott MCMORROW

Inventor： Steve WEIR ,  Scott MCMORROW

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/141 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/0263 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/049 ,  H05K2201/09254 ,  H05K2201/09309 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T307/492

Abstract: A power distribution system for integrated circuits includes methods to damp resonance between a bypass capacitor network and a power/ground cavity of the printed circuit board that (a) does not require excessive quantities of bypass/damping components or (b) does not require high plane cavity capacitance or in the alternative can insure a Q of less than 1.4 at the transition from the bypass network to the plane cavity impedance cross-over.

Abstract translation: 用于集成电路的配电系统包括阻止旁路电容器网络和印刷电路板的电源/接地腔之间的谐振的方法，（a）不需要过量的旁路/阻尼部件，或（b）不需要高 平面腔电容，或者在旁路网络到平面腔阻抗交叉的过渡中，可以确保小于1.4的Q。