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    Initial condition support for partial reconfiguration
    41.
    发明授权
    Initial condition support for partial reconfiguration 有权

    公开(公告)号：US10394990B1

    公开(公告)日：2019-08-27

    申请号：US15277356

    申请日：2016-09-27

    Applicant: Altera Corporation

    Inventor： Kalen Brunham ,  Kevin Nealis ,  Yi Peng ,  Scott Weber

    IPC: G06F17/50

    Abstract: Devices and methods for initializing one or more registers of a programmable integrated circuit (IC) to store an initial condition value are provided. A first bitstream that programs the region of the IC to supply the initial condition value to the one or more registers is first programmed on the IC. Then, once the registers are initialized with the initial condition value, a second bitstream is subsequently programmed to the region of the IC to supply values associated with a function of the design to the one or more registers.

    Multichip package with protocol-configurable data paths
    42.
    发明授权
    Multichip package with protocol-configurable data paths 有权

    公开(公告)号：US10394737B1

    公开(公告)日：2019-08-27

    申请号：US14975270

    申请日：2015-12-18

    Applicant: Altera Corporation

    Inventor： Huy Ngo ,  Keith Duwel ,  David W. Mendel

    IPC: G06F13/00 ,  G06F13/40 ,  G06F13/42 ,  G06F5/06

    Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1x mode or 2x mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

    Incremental register retiming of an integrated circuit design
    43.
    发明授权
    Incremental register retiming of an integrated circuit design 有权

    公开(公告)号：US10387603B2

    公开(公告)日：2019-08-20

    申请号：US16002988

    申请日：2018-06-07

    Applicant: Altera Corporation

    Inventor： Nishanth Sinnadurai ,  Gordon Raymond Chiu

    IPC: G06F17/50

    Abstract: A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design. For example, the circuit design computing equipment may preserve the register retiming solution from the first circuit design implementation for portions of the second circuit design that are outside the region-of-change and incrementally create graphs that allow to incrementally solve the register retiming problem during the second circuit design implementation.

    Integrated circuit applications using partial reconfiguration
    45.
    发明授权
    Integrated circuit applications using partial reconfiguration 有权

    公开(公告)号：US10374609B1

    公开(公告)日：2019-08-06

    申请号：US15425744

    申请日：2017-02-06

    Applicant: ALTERA CORPORATION

    Inventor： Joshua Walstrom ,  Mark Bourgeault

    IPC: H03K19/173 ,  H03K19/177 ,  H03K19/0175 ,  G06F13/40 ,  G06F13/42 ,  G06F21/60

    Abstract: Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Partial reconfiguration functionality of an IC may be used to build reconfigurable application platforms that enable application execution on the IC. These apps may include partial reconfiguration bitstreams that allow ease of access to programming without cumbersome compilation via a set of complex tools. The apps may be acquired via a purchasing website or other mechanism, where the bitstreams may be downloaded to the IC, thus increasing usability of the IC as well providing addition revenue streams.

    Safety features for high level design
    46.
    发明授权
    Safety features for high level design 有权

    公开(公告)号：US10366190B2

    公开(公告)日：2019-07-30

    申请号：US15940881

    申请日：2018-03-29

    Applicant: ALTERA CORPORATION

    Inventor： Adam Titley

    IPC: G06F17/50

    Abstract: This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with the first safety data type, and generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition. The second representation can be provided in a second language and include at least one safety feature for a portion of the circuit design associated with the at least one construct.

    Methods for updating memory maps of a system-on-chip
    50.
    发明授权
    Methods for updating memory maps of a system-on-chip 有权

    公开(公告)号：US10331533B2

    公开(公告)日：2019-06-25

    申请号：US15842752

    申请日：2017-12-14

    Applicant: Altera Corporation

    Inventor： David Alexander Munday ,  Matthew Harbridge Gerlach

    IPC: G06F11/00 ,  G06F11/30 ,  G06F11/32 ,  G06F11/07 ,  G06F11/267

    Abstract: This disclosure relates to techniques for updating a memory map maintained by processing circuitry that is coupled to programmable logic circuitry. One of the techniques may involve detecting reconfiguration of a device component formed on a portion of the programmable logic circuitry using monitoring circuitry. The technique may further include generating a notification event based on the reconfiguration of the device component using the monitoring circuitry. The notification event may then be sent to the processing circuitry using the monitoring circuitry. The technique may further involve updating, using the processing circuitry, the memory map based on the notification event.

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