公开(公告)号：US07360050B2

公开(公告)日：2008-04-15

申请号：US11681375

申请日：2007-03-02

Applicant: Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

Inventor： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

IPC: G06F12/00

CPC classification number: G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

Abstract: An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the device activate a row of memory cells identified by the row address. The write command specifies that the memory device receive write data and store the write data at a location, identified by the column address, in the row of memory cells. The write command is posted internally to the memory device after a first delay has transpired from a first time period in which the write command is received at the second set of pins. The write data is received at a third set of pins after a second delay has transpired from the first time period.

Abstract translation: 集成电路存储器件具有第一组引脚，以使用时钟信号接收行地址，后跟列地址。 器件具有第二组引脚，用于使用时钟信号接收检测命令和写入命令。 sense命令指定设备激活由行地址标识的一行存储器单元。 write命令指定存储器件接收写入数据，并将写入数据存储在由列地址标识的存储单元行中的位置。 在从第二组引脚接收写入命令的第一时间段开始第一个延迟之后，将写入命令内部发布到存储器件。 在从第一时间段开始第二延迟之后，在第三组引脚处接收写入数据。

公开(公告)号：US20070292009A1

公开(公告)日：2007-12-20

申请号：US11845747

申请日：2007-08-27

Applicant: David Nguyen ,  Jim Ni ,  Charles Lee ,  Ming-Shiang Shen

Inventor： David Nguyen ,  Jim Ni ,  Charles Lee ,  Ming-Shiang Shen

IPC: G06K9/00

CPC classification number: G06K9/0002 ,  G06F21/32 ,  G06F21/85 ,  G06F21/86 ,  G06K19/07354 ,  G06K19/07732

Abstract: A pen-type computer peripheral device includes an elongated housing containing a PCBA having a plug connector and a fingerprint sensor mounted thereon. The PCBA is secured to a positioning member that is actuated by way of a press-push button that is exposed through a slot defined in a wall of the housing. By pressing and pushing (sliding) the press-push button along the slot, the fingerprint sensor and the plug connector are moved between a retracted position, in which the fingerprint sensor is positioned inside of the housing and the plug connector is covered by a portion of the housing wall, and a deployed position in which the fingerprint sensor is exposed through the slot and the plug connector extends through a front housing opening such that both the fingerprint sensor and the plug connector are exposed outside of the housing.

Abstract translation: 笔式计算机外围设备包括细长壳体，其包含具有安装在其上的插头连接器和指纹传感器的PCBA。 PCBA被固定到通过按压按钮致动的定位构件，该按压按钮通过限定在壳体的壁中的狭槽暴露。 通过沿着插槽按压（滑动）按压按钮，指纹传感器和插头连接器在指纹传感器位于壳体内部并且插头连接器被覆盖部分的缩回位置之间移动 以及展开位置，其中指纹传感器通过狭槽暴露，并且插头连接器延伸穿过前壳体开口，使得指纹传感器和插头连接器都暴露在壳体外部。

公开(公告)号：US20070198868A1

公开(公告)日：2007-08-23

申请号：US11692162

申请日：2007-03-27

Applicant: Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

Inventor： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

IPC: H04L7/033

CPC classification number: G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

Abstract: A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory device includes a pin coupled to the first interconnect to receive a clock signal. The memory device also includes a first plurality of pins coupled to the second interconnect to receive the write command and read command, and a second plurality of pins coupled to the third interconnect to receive write data and to assert read data. Control information is applied to initiate the write operation after a first predetermined delay time transpires from when the write command is received. During a clock cycle of the clock signal, two bits of read data are conveyed by each pin of the second plurality of pins.

Abstract translation: 存储器系统具有第一，第二和第三互连以及耦合到互连的集成电路存储器件。 第二个互连传送写入命令和读取命令。 第三个互连传送写入数据和读取数据。 集成电路存储器件包括耦合到第一互连的引脚以接收时钟信号。 存储器件还包括耦合到第二互连以接收写入命令和读取命令的第一多个引脚，以及耦合到第三互连以接收写入数据和断言读取数据的第二多个引脚。 应用控制信息以在从接收到写入命令之后发生第一预定延迟时间之后启动写入操作。 在时钟信号的时钟周期期间，第二多个引脚的每个引脚传送两位读取数据。

公开(公告)号：US20070184685A1

公开(公告)日：2007-08-09

申请号：US11682261

申请日：2007-03-05

Applicant: Paul Hsueh ,  Jin Kim ,  Nan Nan ,  David Nguyen ,  Ming-Shiang Shen

Inventor： Paul Hsueh ,  Jin Kim ,  Nan Nan ,  David Nguyen ,  Ming-Shiang Shen

IPC: H05K1/00

CPC classification number: H01R13/629 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

Abstract: A universal serial bus (USB) flash drive pen device for deploying and retracting a USB plug connector having a pusher assembly including a USB flash drive and a USB plug connector, in accordance with an embodiment of the present invention. The USB flash drive pen device further includes a housing assembly at least partially enclosing said pusher assembly for deploying said USB plug connector, said USB flash drive being coupled to said USB plug connector, said pusher assembly retracting said USB plug connector into said housing assembly, said USB flash drive pen device for deploying said USB plug connector to couple said USB flash drive to a USB port.

Abstract translation: 根据本发明的实施例的通用串行总线（USB）闪存驱动笔装置，用于部署和缩回具有包括USB闪存驱动器和USB插头连接器的推动器组件的USB插头连接器。 所述USB闪存驱动器笔装置还包括至少部分地封闭所述推动器组件以用于展开所述USB插头连接器的壳体组件，所述USB闪存驱动器耦合到所述USB插头连接器，所述推动器组件将所述USB插头连接器缩回到所述壳体组件中， 所述USB闪存笔设备用于部署所述USB插头连接器以将所述USB闪存驱动器耦合到USB端口。

公开(公告)号：US07236894B2

公开(公告)日：2007-06-26

申请号：US11021598

申请日：2004-12-23

Applicant: Kyung Suk Oh ,  Frank Lambrecht ,  David Nguyen

Inventor： Kyung Suk Oh ,  Frank Lambrecht ,  David Nguyen

IPC: G11C7/14

CPC classification number: G11C5/147 ,  G01R31/31924 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A circuit, system and method adjusts a reference voltage, such as an internal or external reference voltage VREF, in response to a first voltage at a first contact, such as a pin on a memory controller used for reading or writing data, and a second voltage at a second contact in embodiments. Logic is coupled to the first and second contacts to provide a control signal in response to the first and second voltages. A comparator provides an input signal to the logic in response to a target reference voltage and the reference voltage during a calibration or initialization mode of operation. In an alternate embodiment, a plurality of data values at a first contact are compared to a predetermined plurality of test data. An up/down signal is then provided to a counter and a register stores a counter value used to provide a reference voltage.

Abstract translation: 电路，系统和方法响应于第一触点处的第一电压（例如用于存储器控制器的存储器控​​制器中的引脚）来调整参考电压，诸如内部或外部参考电压V REF， 读取或写入数据，以及第二触点的第二电压。 逻辑耦合到第一和第二触点以响应于第一和第二电压提供控制信号。 比较器在校准或初始化操作模式期间响应于目标参考电压和参考电压向逻辑器提供输入信号。 在替代实施例中，将第一联系人处的多个数据值与预定的多个测试数据进行比较。 然后向计数器提供上/下信号，并且寄存器存储用于提供参考电压的计数器值。

公开(公告)号：US20070120575A1

公开(公告)日：2007-05-31

申请号：US11668422

申请日：2007-01-29

Applicant: Belgacem Haba ,  Richard Perego ,  David Nguyen ,  Billy Garrett ,  Ely Tsern ,  Craig Hampel ,  Wai-Yeung Yip

Inventor： Belgacem Haba ,  Richard Perego ,  David Nguyen ,  Billy Garrett ,  Ely Tsern ,  Craig Hampel ,  Wai-Yeung Yip

IPC: H03K17/16 ,  G11C5/00

CPC classification number: G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

Abstract translation: 公开了可用于实现具有1至N个信道的模块的各种模块结构。 总线系统可以通过这种模块的互连形成。

公开(公告)号：US20070023248A1

公开(公告)日：2007-02-01

申请号：US11461536

申请日：2006-08-01

Applicant: David Nguyen ,  John Hayward

Inventor： David Nguyen ,  John Hayward

IPC: F16D41/08

CPC classification number: F16D41/069 ,  F16D41/084

Abstract: A clutch assembly that includes an input member rotatable about an axis, an output member rotatable about the axis, and an engagement member having a portion between the input and output members. The engagement member is operable to selectively couple the input and output members together for co-rotation. The clutch assembly further includes a blocking member having a base and a projection. The projection is coupled to the engagement member to substantially prevent the engagement member from coupling the input and output members together for co-rotation when the input member rotates in a first direction relative to the output member, while allowing the engagement member to couple the input and output members lor together co-rotation when the input member rotates in a second direction relative to the output member.

Abstract translation: 一种离合器组件，其包括可围绕轴线旋转的输入构件，可围绕该轴线旋转的输出构件以及具有在输入和输出构件之间的部分的接合构件。 接合构件可操作以选择性地将输入和输出构件联接在一起用于共同旋转。 离合器组件还包括具有基部和突起的阻挡构件。 当输入构件相对于输出构件沿第一方向旋转时，凸起联接到接合构件以基本上防止接合构件将输入和输出构件联接在一起用于共同旋转，同时允许接合构件将输入 并且当输入构件相对于输出构件沿第二方向旋转时，输出构件一起共同旋转。

公开(公告)号：US07162376B2

公开(公告)日：2007-01-09

申请号：US11063490

申请日：2005-02-22

Applicant: Kyung Suk Oh ,  Frank Lambrecht ,  David Nguyen

Inventor： Kyung Suk Oh ,  Frank Lambrecht ,  David Nguyen

IPC: G11C7/14

CPC classification number: G11C5/147 ,  G01R31/31924 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A system comprises a master device and a plurality of memory devices coupled to the master device by an interconnect in an embodiment. The master device obtains a plurality of values representing reference voltage values and selects a first value in the plurality of values representing reference voltage values to generate an internal reference voltage value when reading data from a selected memory device in the plurality of memory devices. A method comprises obtaining a plurality of values representing reference voltages for a plurality of memory devices in an embodiment. A first value is selected in the plurality of values representing reference voltages. A reference voltage value is adjusted in response to the first value to an adjusted reference voltage value. Data is transferred to a selected memory device in the plurality of memory devices using the adjusted reference voltage value.

Abstract translation: 在一个实施例中，系统包括主设备和通过互连耦合到主设备的多个存储设备。 主装置获取表示参考电压值的多个值，并且在从多个存储装置中的选定存储装置读取数据时，选择表示参考电压值的多个值中的第一值以产生内部参考电压值。 一种方法包括在一个实施例中获得表示多个存储器件的参考电压的多个值。 在表示参考电压的多个值中选择第一值。 响应于第一值将参考电压值调整到调整的参考电压值。 使用经调整的参考电压值将数据传送到多个存储器件中的选定的存储器件。

公开(公告)号：US20060277345A1

公开(公告)日：2006-12-07

申请号：US11459858

申请日：2006-07-25

Applicant: Haw-Jyh Liaw ,  David Nguyen

Inventor： Haw-Jyh Liaw ,  David Nguyen

IPC: G06F13/14

CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

Abstract: A high frequency bus system insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A first bus segment has one or more devices connected to it between a first and a second end. A second bus segment which has no devices connected to it. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time.

Abstract translation: 尽管在模块和连接器上使用总线，高频总线系统可确保高保真信号到达高频总线上的设备的均匀到达时间。 第一总线段具有在第一和第二端之间连接到它的一个或多个设备。 没有连接设备的第二总线段。 第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本上同时被引入第二总线段的第一端时，它们到达每个设备 在同一时间连接到第一总线段。

公开(公告)号：US20050073294A1

公开(公告)日：2005-04-07

申请号：US10680707

申请日：2003-10-07

Applicant: Donald Baxter ,  Kenneth Wheeler ,  David Nguyen

Inventor： Donald Baxter ,  Kenneth Wheeler ,  David Nguyen

IPC: G01R15/18 ,  G01R19/00 ,  G01R33/00

CPC classification number: G01R15/183 ,  G01R19/003

Abstract: A current control circuit that employs a magnetic amplifier and an active feedback circuit. The feedback circuit establishes the effective operating current of the amplifier at a fixed point. The magnetic amplifier includes a pair of oppositely wound gate windings, a bias winding and a control winding. The gate windings are driven by an oscillator driver that generates a gate winding current and a gate winding voltage. A reference voltage and the gate winding voltage are applied to a feedback amplifier and the feedback circuit. When the gate winding voltage becomes equal to the reference voltage, the feedback circuit is stable and the gate winding current is set to a desired zero current operating point.

Abstract translation: 一种采用磁放大器和有源反馈电路的电流控制电路。 反馈电路在固定点建立放大器的有效工作电流。 磁放大器包括一对相对卷绕的栅极绕组，偏置绕组和控制绕组。 栅极绕组由产生栅极绕组电流和栅极绕组电压的振荡器驱动器驱动。 参考电压和栅极绕组电压被施加到反馈放大器和反馈电路。 当栅极绕组电压变得等于参考电压时，反馈电路是稳定的，并且栅极绕组电流被设置到期望的零电流工作点。