公开(公告)号：US11784650B2

公开(公告)日：2023-10-10

申请号：US17964938

申请日：2022-10-13

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Kang Wei ,  Liang Zhang

IPC: H03L7/081 ,  H03L7/083 ,  H03L7/183

CPC classification number: H03L7/0818 ,  H03L7/083 ,  H03L7/183

Abstract: The application provides a calibration method, a calibration device and a multi-phase clock circuit. The method includes: gating each of multi-phase clock signals as a first primary clock signal and gating a corresponding clock signal as a first auxiliary clock signal according to a first preset rule; gating each of the multi-phase clock signals as a second primary clock signal and gating a corresponding clock signal as a second auxiliary clock signal according to a second preset rule; obtaining a time difference between each primary clock signal and its corresponding auxiliary clock signal under the first preset rule and the second preset rule; determining a delay adjustment amount of each primary clock signal according to the time difference, and obtaining a phase error between the multi-phase clock signals according to the delay adjustment amount; and obtaining a calibration amount of the multi-phase clock signals according to the phase error.

公开(公告)号：US20230289298A1

公开(公告)日：2023-09-14

申请号：US18117489

申请日：2023-03-06

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Mi YANG ,  Yu CAI

IPC: G06F12/109 ,  G06F9/50

CPC classification number: G06F12/109 ,  G06F9/5027 ,  G06F2212/657

Abstract: A method for splitting operators, a device for splitting operators and a non-transitory computer readable storage medium are provided. The method includes: S1: obtaining buffer information required by target operators; and S2: splitting the target operators to obtain a splitting result of the target operators, and obtaining a storage layout of the target operators in the first memory, based on the buffer information required by the target operators and a storage capacity of the first memory; the splitting result of the target operators and the storage layout of the target operators are used to implement a mapping of a target artificial intelligence model to an artificial intelligence hardware accelerator.

公开(公告)号：US11735232B2

公开(公告)日：2023-08-22

申请号：US17202326

申请日：2021-03-15

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Christopher Cox

IPC: G11C5/04 ,  G11C5/14 ,  H05K1/18

CPC classification number: G11C5/147 ,  G11C5/04 ,  H05K1/181 ,  H05K2201/10159

Abstract: A memory device includes a printed circuit board having a plurality of conductive layers; memory chips mounted over the printed circuit board, wherein the memory chips comprise at least a first number of memory chips and a second number of memory chips; a first power module mounted over the printed circuit board and for providing a first set of power supplies to the first number of memory chips through the plurality of conductive layers; and a second power module mounted over the printed circuit board and for providing a second set of power supplies to the second number of memory chips through the plurality of conductive layers.

公开(公告)号：US20230153153A1

公开(公告)日：2023-05-18

申请号：US18056242

申请日：2022-11-16

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Yanjia KE ,  Zhaohui DU ,  Wenbo QU

IPC: G06F9/48 ,  G06F9/445 ,  G06F9/30

CPC classification number: G06F9/4881 ,  G06F9/44505 ,  G06F9/3004

Abstract: A task processing apparatus and a task processing method are provided. The task processing apparatus is coupled to a host apparatus, and includes: a controller configured to query whether there is a data processing task to be executed and trigger execution of the data processing task; at least one data processing engine configured to process operation data corresponding to the data processing task according to a configured working mode, and generate a data processing result; and at least one scheduler configured to: receive a task descriptor of the data processing task from the host apparatus; configure the working mode of the data processing engine based on the task descriptor; control transmission of the operation data corresponding to the data processing task from the host apparatus to the data processing engine; and control transmission of the data processing result from the data processing engine to the host apparatus.

公开(公告)号：US20230121503A1

公开(公告)日：2023-04-20

申请号：US17964938

申请日：2022-10-13

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Kang WEI ,  Liang ZHANG

IPC: H03L7/081 ,  H03L7/183 ,  H03L7/083

Abstract: The application provides a calibration method, a calibration device and a multi-phase clock circuit. The method includes: gating each of multi-phase clock signals as a first primary clock signal and gating a corresponding clock signal as a first auxiliary clock signal according to a first preset rule; gating each of the multi-phase clock signals as a second primary clock signal and gating a corresponding clock signal as a second auxiliary clock signal according to a second preset rule; obtaining a time difference between each primary clock signal and its corresponding auxiliary clock signal under the first preset rule and the second preset rule; determining a delay adjustment amount of each primary clock signal according to the time difference, and obtaining a phase error between the multi-phase clock signals according to the delay adjustment amount; and obtaining a calibration amount of the multi-phase clock signals according to the phase error.

公开(公告)号：US20220376495A1

公开(公告)日：2022-11-24

申请号：US17458498

申请日：2021-08-26

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Chunlai SUN ,  Juan DU

IPC: H02H9/04 ,  H03K19/003 ,  H03K19/00 ,  H03K19/0944

Abstract: The present disclosure provides an SST driving circuit, a chip, and a driving output method. The SST driving circuit includes: a signal driver for driving and outputting a signal to be driven, the signal driver including termination resistors; a first electrostatic current discharge module, providing first discharge paths for electrostatic currents generated in the signal driver; a second electrostatic current discharge module, connected in series with the termination resistors, providing second discharge paths for the electrostatic currents; and a power clamp, used for conducting the power clamp circuit, the first discharge paths and the second discharge paths when a power supply voltage of the signal driver exceeds a clamping voltage. The present disclosure provides different discharge paths, which effectively reduces voltage borne by a protected device through a voltage division method, and improves the device's ability to protect against electrostatic discharge.

公开(公告)号：US20220334762A1

公开(公告)日：2022-10-20

申请号：US17709454

申请日：2022-03-31

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Jie DAI ,  Chunyi LI ,  Zhijie LIU ,  Zhongyuan CHANG

IPC: G06F3/06

Abstract: The application discloses a device and a method for picking up top k values from N values. The method comprises: A) controlling a buffer to receive values into a data pool until the number of values in the data pool reaches the predetermined memory size; B) dividing the values in the data pool into a first portion and a second portion based on their comparison to an adjustable threshold value until the number of values in the first portion falls into a predetermined range; C) discarding the values in the second portion and controlling the buffer to continue to receive values into the data pool until the number of values in the data pool reaches the predetermined memory size again or the buffer has received all the N values; D) repeating steps B to C until the buffer has received all the N values; E) dividing the values in the data pool into the first portion and the second portion based on their comparison to the adjustable threshold value, until the number of values in the first portion reaches k; and F) controlling the buffer to output the k values in the first portion as the top k values.

公开(公告)号：US11157183B2

公开(公告)日：2021-10-26

申请号：US16721936

申请日：2019-12-20

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Howard Chonghe Yang ,  Zhongyuan Chang ,  Chunyi Li

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40

Abstract: The application discloses a memory controller coupled to a memory module for controlling access to the memory module. The memory controller comprises: a registering clock driver coupled to the memory module for providing a data access command to the memory module so as to control access to the memory module; and a data buffer coupled between the registering clock driver and the memory module for exchanging data between the memory module and the registering clock driver under the control of the registering clock driver; wherein the registering clock driver comprises a computing unit for computing the data received via the data buffer from the memory module and providing a computing result to the memory module via the data buffer.

公开(公告)号：US20210313005A1

公开(公告)日：2021-10-07

申请号：US16914457

申请日：2020-06-28

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Gang SHAN ,  Yong ZHANG

IPC: G11C29/00 ,  G06F3/06 ,  G11C29/38

Abstract: The present application discloses an apparatus for repairing a defect of a memory module, comprises: a central buffer having an address recording module for recording defective address information indicating one or more defective memory addresses in the memory module; the central buffer is configured to receive an access command for accessing a target address in the memory module from a memory interface, and to determine whether to generate a repair access command for repairing the target address according to a comparison result; and a data buffer having a data recording module for recording repair data; wherein the data buffer is coupled between the memory interface and the memory module to buffer data interacted therebetween, and is coupled to the central buffer to receive the access command or the repair access command; the data buffer is configured to write target data associated with the access command into the data recording module as repair data corresponding to a target address according to the repair access command, or read repair data from the data recording module as target data corresponding to a target address.

公开(公告)号：US10929029B2

公开(公告)日：2021-02-23

申请号：US16239542

申请日：2019-01-04

Applicant: MONTAGE TECHNOLOGY CO., LTD.

Inventor： Gang Shan ,  Howard Chonghe Yang ,  Yi Li

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/08

Abstract: A memory controller and a method for accessing a memory module are provided. The memory controller is coupled between the memory module and a host controller to control the access of the host controller to the memory module. The memory controller comprises: a central buffer coupled to the host controller for receiving a data access command from the host controller, and coupled to the memory module for providing a modified data access command to the memory module; wherein the central buffer comprises an access command processing module, for processing the data access command to generate the modified data access command; and a data buffer coupled to the central buffer for receiving the modified data access command from the central buffer, and coupled between the host controller and the memory module for exchanging data between the host controller and the memory module under the control of the modified data access command.