Abstract:
A method for forming a nitrided tunnel oxide layer is described. A silicon oxide layer as a tunnel oxide layer is formed on a semiconductor substrate, and a plasma nitridation process is performed to implant nitrogen atoms into the silicon oxide layer. A thermal drive-in process is then performed to diffuse the implanted nitrogen atoms across the silicon oxide layer.
Abstract:
This disclosure concerns methods for ion implantation of semiconductor devices such as VCSELs. In on example of such a method, a surface of the semiconductor structure is disposed at a predetermined orientation. The semiconductor structure is then rotated at a predetermined speed. An ion beam of characteristic flux is generated and directed at the surface of the semiconductor structure so that the ion beam is incident on the surface at an incident flux angle. Because the ion beam is incident on the surface at a defined angle, an implant region having an approximately wedge shaped cross-section is formed in the semiconductor device.
Abstract:
A vertical cavity emitting laser (VCSEL) having a tunnel junction. The junction may be isolated with an implant into a top mirror and past the junction and p-layer. A trench around the VCSEL may result in reduced capacitance and more D.C. isolation of the junction. The implant may occur after the trench is made. Some implant may pass the trench to a bottom mirror. Additional isolation and current confinement may be provided with lateral oxidation of a layer below the junction. Internal trenches may be made from the top of the VCSEL vertically to an oxidizable layer below the junction. For further isolation, an open trench may be placed around a bonding pad and its bridge to the VCSEL and internal vertical trenches may be placed on the pad and its bridge down to the oxidizable layer.
Abstract:
A graded optical element is provided that includes graded layers of optical material, wherein the layers may or may not have different indexes of refraction. A method for making such a graded thickness optical element is also provided. A masking layer is preferably spaced above a substrate, where the masking layer has at least one aperture therein. Optical material is then deposited on the substrate through the aperture in the masking layer to form a layer of refr material that extends laterally beyond the aperture in the masking layer in at least one region.
Abstract:
A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity. Further, wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route.
Abstract:
A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.
Abstract:
A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.
Abstract:
A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity. Further, wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route.
Abstract:
One embodiment includes a method that includes scanning a plurality of specimens with a laser by moving the laser according to coordinates for laser movement and measuring a distance for each of the plurality of specimens, associating location information with each of the specimens of the plurality of specimens based on its distance from the laser and its coordinates for laser movement, recording a Raman spectrum for the plurality of specimens, associating a Raman spectrum with each specimen of the plurality of specimens and indicating a Raman spectrum and location information for at least one specimen.