公开(公告)号：US20200373312A1

公开(公告)日：2020-11-26

申请号：US16636199

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma

IPC: H01L27/11507 ,  G11C11/22 ,  G11C8/14 ,  G11C7/18 ,  H01L29/423

Abstract: An integrated circuit includes a backend thin-film transistor (TFT) a ferroelectric capacitor electrically connected to the backend TFT. The backend TFT has a gate electrode, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, and a gate dielectric between the gate electrode and semiconductor region. The ferroelectric capacitor has a first terminal electrically connected to one of the source and drain regions, a second terminal, and a ferroelectric dielectric between the first and second terminals. In an embodiment, a memory cell includes this integrated circuit, the gate electrode being electrically connected to a wordline, the source region being electrically coupled to a bitline, and the drain region being the one of the source and drain regions. In an embodiment, an embedded memory includes wordlines, bitlines, and a plurality of such memory cells at crossing regions of the wordlines and bitlines.

公开(公告)号：US10818799B2

公开(公告)日：2020-10-27

申请号：US16461331

申请日：2016-12-24

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert W. Dewey ,  Willy Rachmady

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/22 ,  H01L27/24 ,  H01L29/423 ,  H01L29/66

Abstract: Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.

公开(公告)号：US20200312846A1

公开(公告)日：2020-10-01

申请号：US16649799

申请日：2017-12-29

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Abhishek A. Sharma ,  Ravi Pillarisetty ,  Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak ,  Gilbert Dewey ,  Cheng-Ying Huang

IPC: H01L27/092 ,  H01L29/20 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

Abstract: An integrated circuit includes: a germanium-containing fin structure above a layer of insulation material; a group III-V semiconductor material containing fin structure above the layer of insulation material; a first gate structure on a portion of the germanium-containing fin structure; a second gate structure on a portion of the group III-V semiconductor material containing fin structure; a first S/D region above the layer of insulation material and laterally adjacent to the portion of the germanium-containing fin structure, the first S/D region comprising a p-type impurity and at least one of silicon or germanium; a second S/D region above the layer of insulation material and laterally adjacent to the portion of the group III-V semiconductor material containing fin structure, the second S/D region comprising an n-type impurity and a second group III-V semiconductor material; and a layer comprising germanium between the layer of insulation material and the second S/D region.

公开(公告)号：US20200235246A1

公开(公告)日：2020-07-23

申请号：US16647679

申请日：2018-01-10

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Li Huey Tan ,  Tristan A. Tronic ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/20 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: Techniques are disclosed for forming thin-film transistors (TFTs) with low contact resistance. As disclosed in the present application, the low contact resistance can be achieved by intentionally thinning one or both of the source/drain (S/D) regions of the thin-film layer of the TFT device. As the TFT layer may have an initial thickness in the range of 20-65 nm, the techniques for thinning the S/D regions of the TFT layer described herein may reduce the thickness in one or both of those S/D regions to a resulting thickness of 3-10 nm, for example. Intentionally thinning one or both of the S/D regions of the TFT layer induces more electrostatic charges inside the thinned S/D region, thereby increasing the effective dopant in that S/D region. The increase in effective dopant in the thinned S/D region helps lower the related contact resistance, thereby leading to enhanced overall device performance.

公开(公告)号：US20200235105A1

公开(公告)日：2020-07-23

申请号：US16633061

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi

IPC: H01L27/11 ,  G11C11/419 ,  G11C5/06 ,  G11C5/10

Abstract: A 2T-2S SRAM cell exhibiting a complementary scheme, that includes two selector devices that exhibit negative differential resistance. Advantages include lower area and better performance than traditional SRAM cells, according to some embodiments. The term 1T-1S refers to a transistor in series with a selector device. Accordingly, the term 2T-2S refers to two such 1T-1S structures.

公开(公告)号：US20200099509A1

公开(公告)日：2020-03-26

申请号：US16140918

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Willy Rachmady ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H04L9/06 ,  H04L9/08 ,  G06F12/0862 ,  G06F12/0875 ,  G06F3/06 ,  G06F9/30

Abstract: A stacked-substrate advanced encryption standard (AES) integrated circuit device is described in which at least some circuits associated logic functions (e.g., AES encryption operations, memory cell access and control) are provided on a first substrate. Memory arrays used with the AES integrated circuit device (sometimes referred to as “embedded memory”) are provided on a second substrate stacked on the first substrate, thus forming a AES integrated circuit device on a stacked-substrate assembly. Vias are fabricated to pass through the second substrate, into a dielectric layer between the first substrate and the second substrate, and electrically connect to conductive interconnections of the AES logic circuits.

公开(公告)号：US20200035839A1

公开(公告)日：2020-01-30

申请号：US16043593

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Van H. Le ,  Abhishek A. Sharma ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Miriam R. Reshotko ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are transistor gate-channel arrangements that may be implemented in nanowire thin film transistors (TFTs) with textured semiconductors, and related methods and devices. An example transistor gate-channel arrangement may include a substrate, a channel material that includes a textured thin film semiconductor material shaped as a nanowire, a gate dielectric that at least partially wraps around the nanowire, and a gate electrode material that wraps around the gate dielectric. Implementing textured thin film semiconductor channel materials shaped as a nanowire and having a gate stack of a gate dielectric and a gate electrode material wrapping around the nanowire advantageously allows realizing gate all-around or bottom-gate transistor architectures for TFTs with textured semiconductor channel materials.

公开(公告)号：US20200027883A1

公开(公告)日：2020-01-23

申请号：US16495600

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Van H. Le ,  Abhishek A. Sharma ,  Ravi Pillarisetty ,  Gilbert W. Dewey ,  Shriram Shivaraman ,  Tristan A. Tronic ,  Sanaz Gardner ,  Tahir Ghani

IPC: H01L27/108 ,  H01L29/786 ,  H01L27/12

Abstract: Substrates, assemblies, and techniques for an apparatus, where the apparatus includes a gate, where the gate includes a first gate side and a second gate side opposite to the first gate side, a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite to the first gate dielectric side, a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side, a channel, where the gate dielectric is between the channel and the gate, a source coupled with the channel, and a drain coupled with the channel, where the first dielectric abuts the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.

公开(公告)号：US20190326403A1

公开(公告)日：2019-10-24

申请号：US15956604

申请日：2018-04-18

Applicant: INTEL CORPORATION

Inventor： Ravi Pillarisetty ,  Prashant Majhi ,  Abhishek A. Sharma ,  Elijah V. Karpov ,  Brian S. Doyle ,  Willy Rachmady ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L29/24 ,  H01L29/861 ,  G01K7/34 ,  H01L29/16 ,  H01L29/20

Abstract: Electronic devices, integrated circuit device structures, and computing devices including thin film, diode-based temperature sensors are disclosed. An electronic device includes a diode including diode materials between a first contact and a second contact, a device layer of an integrated circuit device structure, and at least a portion of an interlayer dielectric between the diode and the device layer.

公开(公告)号：US20190305121A1

公开(公告)日：2019-10-03

申请号：US15939087

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Gilbert Dewey ,  Van H. Le ,  Willy Rachmady ,  Ravi Pillarisetty

IPC: H01L29/778 ,  H01L29/267 ,  H01L29/66

Abstract: Techniques and mechanisms for providing efficient transistor functionality of an integrated circuit. In an embodiment, a transistor device comprises a first body of a high mobility semiconductor and a second body of a wide bandgap semiconductor. The first body adjoins each of, and is disposed between, the second body and a gate dielectric layer of the transistor. The second body extends between, and variously adjoins, each of a source of the transistor and a drain of the transistor. A location of the second body mitigates current leakage that might otherwise occur via the first body. In another embodiment, a mobility of the first body is equal to or greater than 100 cm2/V·s, wherein a bandgap of the second body is equal to or greater than 2.0 eV.