公开(公告)号：US20170288639A1

公开(公告)日：2017-10-05

申请号：US15088830

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Feras EID ,  Baris BICEN ,  Telesphor KAMGAING ,  Vijay K. NAIR ,  Georgios C. DOGIAMIS ,  Johanna M. SWAN ,  Valluri R. RAO

IPC: H03H9/30 ,  H03H9/13

Abstract: Embodiments of the invention include a waveguide structure that includes a first piezoelectric transducer that is positioned in proximity to a first end of a cavity of an organic substrate. The first piezoelectric transducer receives an input electrical signal and generates an acoustic wave to be transmitted with a transmission medium. A second piezoelectric transducer is positioned in proximity to a second end of the cavity. The second piezoelectric transducer receives the acoustic wave from the transmission medium and generates an output electrical signal.

公开(公告)号：US20170283249A1

公开(公告)日：2017-10-05

申请号：US15088982

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Feras EID ,  Adel A. ELSHERBINI ,  Vijay K. NAIR ,  Telesphor KAMGAING ,  Valluri R. RAO ,  Johanna M. SWAN

IPC: B81B7/00

CPC classification number: B81C1/0015 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/04

Abstract: Embodiments of the invention include a switching device that includes an electrode, a piezoelectric material coupled to the electrode, and a movable structure (e.g., cantilever, beam) coupled to the piezoelectric material. The movable structure includes a first end coupled to an anchor of a package substrate having organic layers and a second released end positioned within a cavity of the package substrate.

公开(公告)号：US20230343716A1

公开(公告)日：2023-10-26

申请号：US18216102

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Amr ELSHAZLY ,  Arun CHANDRASEKHAR ,  Shawna M. LIFF ,  Johanna M. SWAN

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L25/00 ,  H01L2224/16225 ,  H01L2224/1703

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

公开(公告)号：US20220415839A1

公开(公告)日：2022-12-29

申请号：US17357722

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Feras EID ,  Johanna M. SWAN ,  Adel A. ELSHERBINI ,  Shawna M. LIFF

IPC: H01L23/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include semiconductor dies with hybrid bonding layers and multi-die modules that are coupled together by hybrid bonding layers. In an embodiment, a semiconductor die comprises a die substrate, a pad layer over the die substrate, where the pad layer comprises first pads with a first dimension and a first pitch and second pads with a second dimension and a second pitch. In an embodiment, the semiconductor die further comprises a hybrid bonding layer over the pad layer. In an embodiment, the hybrid bonding layer comprises a dielectric layer, and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads comprise a third dimension and a third pitch.

公开(公告)号：US20220407205A1

公开(公告)日：2022-12-22

申请号：US17349774

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Neelam PRABHU GAUNKAR ,  Georgios C. DOGIAMIS ,  Johanna M. SWAN

IPC: H01P3/16 ,  H01Q9/04 ,  H01Q1/22 ,  H01P11/00 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to contactless transmission within a package that combines radiating elements with vertical transitions in the package, in particular to a waveguide within a core of the package that is surrounded by a metal ring. A radiating element on one side of the substrate core and above the waveguide surrounded by the metal ring communicates with another radiating element on the other side of the substrate core and below the waveguide surrounded by the metal ring. Other embodiments may be described and/or claimed.

公开(公告)号：US20220406721A1

公开(公告)日：2022-12-22

申请号：US17350152

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Johanna M. SWAN

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/15 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to via structures and/or planar structures within a glass core of a substrate to facilitate high-speed signaling with a die coupled with the substrate. In embodiments, the substrate may be coupled with an interposer to enable high-speed signaling between a compute die (or tile) and a storage die (or tile) that may be remote to the substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20220102344A1

公开(公告)日：2022-03-31

申请号：US17033509

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/092 ,  H01L29/40 ,  H01L27/06 ,  H01L29/20 ,  H01L29/06 ,  H01L23/538

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20220102339A1

公开(公告)日：2022-03-31

申请号：US17033513

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pratik KOIRALA ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Adel A. ELSHERBINI ,  Tushar TALUKDAR ,  Johanna M. SWAN ,  Wilfred GOMES ,  Robert S. CHAU ,  Beomseok CHOI

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778 ,  H01L21/765 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20210193583A1

公开(公告)日：2021-06-24

申请号：US17192462

申请日：2021-03-04

Applicant: INTEL CORPORATION

Inventor： Adel A. ELSHERBINI ,  Johanna M. SWAN ,  Shawna M. LIFF ,  Henning BRAUNISCH ,  Krishna BHARATH ,  Javier SOTO GONZALEZ ,  Javier A. FALCON

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/03 ,  H01L23/498

Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

公开(公告)号：US20200273839A1

公开(公告)日：2020-08-27

申请号：US16647863

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.