公开(公告)号：US20210082797A1

公开(公告)日：2021-03-18

申请号：US16642770

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Kyu Oh Lee ,  Dilan Seneviratne ,  Ravindranadh T. Eluri

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first via, and a second via. The bridge interconnect may include a bridge interconnect first side with a conductive pad and a bridge interconnect second side. The distance between the bridge interconnect first side and the semiconductor package first side may be less than a distance between the bridge interconnect second side and the semiconductor package first side. The first and second vias may each include a first end that is narrower than a second end. The semiconductor package first side may be closer to the first end of the first via than the second end of the first via, and closer to the second end of the second via than the first end of the second via. The first side of the semiconductor package may be configured to electrically couple to a die.

公开(公告)号：US20200251467A1

公开(公告)日：2020-08-06

申请号：US16855376

申请日：2020-04-22

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Rahul Jain ,  Seo Young Kim ,  Kyu Oh Lee ,  Ji Yong Park ,  Sai Vadlamani ,  Junnan Zhao

IPC: H01L27/07 ,  H01L49/02 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00

Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

公开(公告)号：US10692847B2

公开(公告)日：2020-06-23

申请号：US15755533

申请日：2015-08-31

Applicant: Intel Corporation

Inventor： Daniel Sobieski ,  Kristof Darmawikarta ,  Sri Ranga Sai Boyapati ,  Merve Celikkol ,  Kyu Oh Lee ,  Kemal Aygun ,  Zhiguo Qian

IPC: H01L25/18 ,  H01L23/14 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00

Abstract: Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry.

公开(公告)号：US20200066543A1

公开(公告)日：2020-02-27

申请号：US16113109

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Sai Vadlamani ,  Junnan Zhao ,  Ji Yong Park ,  Kyu Oh Lee ,  Cheng Xu

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31

Abstract: Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

公开(公告)号：US20200006210A1

公开(公告)日：2020-01-02

申请号：US16019807

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park

IPC: H01L23/498 ,  H01L21/48

Abstract: A chip package that includes a die coupled to a package substrate. The substrate includes a first ground layer and a dielectric material engaging the first ground layer. A solder resist layer engages the dielectric material and a routing layer is disposed at least partially within the solder resist layer. A second ground layer engages the solder resist layer.

公开(公告)号：US20190198436A1

公开(公告)日：2019-06-27

申请号：US15855453

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Robert A. May ,  Rahul S. Jain ,  Lauren A. Link ,  Andrew J. Brown ,  Kyu Oh Lee ,  Sheng C. Li

IPC: H01L23/498 ,  H01L21/48 ,  H01F27/28 ,  H01F41/04 ,  H01F27/40

CPC classification number: H01L23/49838 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/043 ,  H01F2027/2809 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/16157 ,  H01L2924/19042 ,  H01L2924/19102

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

公开(公告)号：US10121752B2

公开(公告)日：2018-11-06

申请号：US15545670

申请日：2015-02-25

Applicant: INTEL CORPORATION

Inventor： Srinivas V. Pietambaram ,  Kyu Oh Lee

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/00 ,  C22C19/03 ,  H01L23/498

Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.

公开(公告)号：US10026691B2

公开(公告)日：2018-07-17

申请号：US15180994

申请日：2016-06-13

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Kyu Oh Lee ,  Daniel Nicholas Sobieski

IPC: H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L21/033

Abstract: Package substrates including conductive interconnects having noncircular cross-sections, and integrated circuit packages incorporating such package substrates, are described. In an example, a conductive pillar having a noncircular pillar cross-section is electrically connected to an escape line routing layer. The escape line routing layer may include several series of conductive pads having noncircular pad cross-sections. Accordingly, conductive traces, e.g., strip line escapes and microstrip escapes, may be routed between the series of conductive pads in a single escape line routing layer.

公开(公告)号：US20180019219A1

公开(公告)日：2018-01-18

申请号：US15545670

申请日：2015-02-25

Applicant: INTEL CORPORATION

Inventor： Srinivas V. Pietambaram ,  Kyu Oh Lee

IPC: H01L23/00 ,  B23K35/26 ,  H01L23/498 ,  C22C13/00 ,  C22C19/03

CPC classification number: H01L24/05 ,  B23K35/262 ,  C22C13/00 ,  C22C19/03 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05564 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/0568 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81444 ,  H01L2924/01015 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.

公开(公告)号：US20170318669A1

公开(公告)日：2017-11-02

申请号：US15649830

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Daniel Sobieski ,  Kyu Oh Lee ,  Sri Ranga Sai Boyapati

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/113 ,  H05K3/0041 ,  H05K3/181 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09218 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/096 ,  H05K2201/09654 ,  H05K2203/0548

Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.