公开(公告)号：US10388777B2

公开(公告)日：2019-08-20

申请号：US15574817

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Robert S. Chau

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L21/02 ,  H01L21/8258 ,  H01L27/085 ,  H01L21/04 ,  H01L29/78

Abstract: Crystalline heterostructures including an elevated crystalline structure extending from one or more trenches in a trench layer disposed over a crystalline substrate are described. In some embodiments, an interfacial layer is disposed over a silicon substrate surface. The interfacial layer facilitates growth of the elevated structure from a bottom of the trench at growth temperatures that may otherwise degrade the substrate surface and induce more defects in the elevated structure. The trench layer may be disposed over the interfacial layer with a trench bottom exposing a portion of the interfacial layer. Arbitrarily large merged crystal structures having low defect density surfaces may be overgrown from the trenches. Devices, such as III-N transistors, may be further formed on the raised crystalline structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate.

公开(公告)号：US20190190489A1

公开(公告)日：2019-06-20

申请号：US16327712

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Sansaptak Dasgupta ,  Bruce A. Block ,  Paul B. Fischer ,  Han Wui Then ,  Marko Radosavljevic

IPC: H03H9/205 ,  H03H9/02

CPC classification number: H03H9/205 ,  H03H9/02007 ,  H03H9/02543 ,  H03H9/02574 ,  H03H9/13 ,  H03H9/15 ,  H03H9/172 ,  H03H2009/02173

Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices having multiple resonator thicknesses on a common substrate. A piezoelectric stack is formed in an STI trench and overgrown onto the STI material. In some cases, the piezoelectric stack can include epitaxially grown AlN. In some cases, the piezoelectric stack can include single crystal (epitaxial) AlN in combination with polycrystalline (e.g., sputtered) AlN. The piezoelectric stack thus forms a central portion having a first resonator thickness and end wings extending from the central portion having a different resonator thickness. Each wing may also have different thicknesses. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate. The end wings can have metal electrodes formed thereon, and the central portion can have a plurality of IDT electrodes patterned thereon.

公开(公告)号：US20190190488A1

公开(公告)日：2019-06-20

申请号：US16327705

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Sansaptak Dasgupta ,  Bruce A. Block ,  Paul B. Fischer ,  Han Wui Then ,  Marko Radosavljevic

IPC: H03H9/205 ,  H03H9/02

CPC classification number: H03H9/205 ,  H03H3/04 ,  H03H9/02007 ,  H03H9/175 ,  H03H2003/025 ,  H03H2003/0435 ,  H03H2009/02173

Abstract: Techniques are disclosed for forming integrated circuit film bulk acoustic resonator (FBAR) devices having multiple resonator thicknesses on a common substrate. A piezoelectric stack is formed in an STI trench and overgrown onto the STI material. In some cases, the piezoelectric stack can include epitaxially grown AlN. In some cases, the piezoelectric stack can include single crystal (epitaxial) AlN in combination with polycrystalline (e.g., sputtered) AlN. The piezoelectric stack thus forms a central portion having a first resonator thickness and end wings extending from the central portion and having a different resonator thickness. Each wing may also have different thicknesses from one another. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate. The end wings can have metal electrodes formed thereon, and the central portion can have a plurality of IDT electrodes patterned thereon.

公开(公告)号：US20190181265A1

公开(公告)日：2019-06-13

申请号：US16321356

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Han Wui Then

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/092

Abstract: Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate.

公开(公告)号：US10236369B2

公开(公告)日：2019-03-19

申请号：US15790907

申请日：2017-10-23

Applicant: INTEL CORPORATION

Inventor： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been Y. Jin ,  Robert S. Chau

IPC: H01L29/775 ,  B82Y10/00 ,  H01L29/267 ,  H01L29/66 ,  H01L29/778 ,  H01L21/76 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/15 ,  H01L29/51 ,  H01L29/165

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

公开(公告)号：US10229991B2

公开(公告)日：2019-03-12

申请号：US15505911

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz K. Gardner ,  Marko Radosavljevic ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L29/06

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

公开(公告)号：US20190058041A1

公开(公告)日：2019-02-21

申请号：US16079337

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic

IPC: H01L29/20 ,  H01L27/092 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L21/02 ,  H01L21/8238

Abstract: A gallium nitride transistor can include a silicon substrate and a first oxide layer and a second oxide layer on the substrate. A first gallium nitride layer may reside on the silicon substrate and the first and second oxide layers. A polarization layer may reside on the first gallium nitride layer. A two dimensional electron gas may exist in the first gallium nitride layer proximate to the polarization layer. A second gallium nitride layer may reside on a first sidewall of the polarization layer and on the first oxide layer on the substrate. A first p-doped gallium nitride layer may reside on the second gallium nitride layer. A third gallium nitride layer may reside on a second sidewall of the polarization layer and on the second oxide layer on the substrate. A second p-doped gallium nitride layer may reside on the second gallium nitride layer.

公开(公告)号：US10181518B2

公开(公告)日：2019-01-15

申请号：US15464888

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Niti Goel ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L29/205 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

公开(公告)号：US10177249B2

公开(公告)日：2019-01-08

申请号：US15644488

申请日：2017-07-07

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/778 ,  H01L29/775 ,  H01L29/417 ,  H01L29/15 ,  H01L29/201 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51

Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

公开(公告)号：US10096682B2

公开(公告)日：2018-10-09

申请号：US15464931

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sherry Taft ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L27/108 ,  H01L29/20 ,  H01L21/02 ,  H01L21/762 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8258

Abstract: A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.