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公开(公告)号：US20230326140A1
公开(公告)日：2023-10-12
申请号：US18208805
申请日：2023-06-12
Applicant: Imagination Technologies Limited
Inventor： John W. Howson
CPC classification number: G06T17/20 , G06F9/3885 , G06T1/20 , G06T15/10
Abstract: Methods and tessellation modules for tessellating a patch to generate tessellated geometry data representing the tessellated patch. Received geometry data representing a patch is processed to identify tessellation factors of the patch. Based on the identified tessellation factors of the patch, tessellation instances to be used in tessellating the patch are determined. The tessellation instances are allocated amongst a plurality of tessellation pipelines that operate in parallel, wherein a respective set of one or more of the tessellation instances is allocated to each of the tessellation pipelines, and wherein each of the tessellation pipelines generates tessellated geometry data associated with the respective allocated set of one or more of the tessellation instances.
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公开(公告)号：US20230326118A1
公开(公告)日：2023-10-12
申请号：US18208676
申请日：2023-06-12
Applicant: Imagination Technologies Limited
Inventor： John W. Howson , Aroun Demeure , Steven Fishwick
Abstract: Methods of rendering a scene in a graphics system identify a draw call within a current render and analyse the last shader in the series of shaders used by the draw call to identify any buffers that are sampled by the last shader and that are to be written by a previous render that has not yet been sent for execution on the GPU. If any such buffers are identified, further analysis is performed to determine whether the last shader samples from the identified buffers using screen space coordinates that correspond to a current fragment location and if this determination is positive, the draw call is added to data relating to the previous render and the last shader is recompiled to replace an instruction that reads data from an identified buffer with an instruction that reads data from an on-chip register.
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公开(公告)号：US11676339B2
公开(公告)日：2023-06-13
申请号：US17748982
申请日：2022-05-19
Applicant: Imagination Technologies Limited
Inventor： John W. Howson
CPC classification number: G06T17/20 , G06F9/3885 , G06T1/20 , G06T15/10
Abstract: Methods and tessellation modules for tessellating a patch to generate tessellated geometry data representing the tessellated patch. Received geometry data representing a patch is processed to identify tessellation factors of the patch. Based on the identified tessellation factors of the patch, tessellation instances to be used in tessellating the patch are determined. The tessellation instances are allocated amongst a plurality of tessellation pipelines that operate in parallel, wherein a respective set of one or more of the tessellation instances is allocated to each of the tessellation pipelines, and wherein each of the tessellation pipelines generates tessellated geometry data associated with the respective allocated set of one or more of the tessellation instances.
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44.发明公开公开(公告)号：US20230154108A1
公开(公告)日：2023-05-18
申请号：US18093786
申请日：2023-01-05
Applicant: Imagination Technologies Limited
Inventor： John W. Howson
CPC classification number: G06T17/10 , G06T15/005 , G06T11/40 , G06T1/0007
Abstract: Methods and apparatus for generating a data structure for storing primitive data for a number of primitives and vertex data for a plurality of vertices, wherein each primitive is defined with reference to one or more of the plurality of vertices. The vertex data comprises data for more than one view, such as a left view and a right view, with vertex parameter values for a first group of vertex parameters being stored separately for each view and vertex parameter values for a second, non-overlapping group of vertex parameters being stored only once and used when rendering either or both views.
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公开(公告)号：US11600034B2
公开(公告)日：2023-03-07
申请号：US17170590
申请日：2021-02-08
Applicant: Imagination Technologies Limited
Inventor： Diego Jesus , John W. Howson , Panagiotis Velentzas , Robert Brigg , Xile Yang
Abstract: Methods and control stream generators for generating a control stream for a tile group comprising at least two tiles, the control stream identifying primitive blocks that are relevant to rendering at least one tile in the tile group. The method includes: receiving information identifying one or more primitive blocks relevant to rendering at least one tile in the tile group, each primitive block comprising one or more primitives; generating a primitive block entry for each of the identified primitive blocks; and adding each primitive block entry to the control stream; wherein generating the primitive block entry for at least one of the identified primitive blocks comprises: (i) identifying a bounding box encompassing the one or more primitives of the primitive block; (ii) generating a coverage mask that indicates which tiles of the tile group that intersect the bounding box for the primitive block are valid for the primitive block, a tile being valid for a primitive block if at least one primitive of the primitive blocks falls, at least partially, within the bounds of the tile; and (iii) including the coverage mask in the primitive block entry.
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Patent Agency Ranking
公开(公告)号：US11587282B2
公开(公告)日：2023-02-21
申请号：US17181287
申请日：2021-02-22
Applicant: Imagination Technologies Limited
Inventor： Gregory Clark , John W. Howson , Justin DeCell , Steven J. Clohset
IPC: G06T15/06 , G06F30/327 , G06T17/00
Abstract: Methods and ray tracing units are provided for performing intersection testing for use in rendering an image of a 3-D scene. A hierarchical acceleration structure may be traversed by traversing one or more upper levels of nodes of the hierarchical acceleration structure according to a first traversal technique, the first traversal technique being a depth-first traversal technique; and traversing one or more lower levels of nodes of the hierarchical acceleration structure according to a second traversal technique, the second traversal technique not being a depth-first traversal technique. Results of traversing the hierarchical acceleration structure are used for rendering the image of the 3-D scene. The upper levels of the acceleration structure may be defined according to a spatial subdivision structure, whereas the lower levels of the acceleration structure may be defined according to a bounding volume structure.
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47.发明授权公开(公告)号：US11562533B2
公开(公告)日：2023-01-24
申请号：US17086680
申请日：2020-11-02
Applicant: Imagination Technologies Limited
Inventor： John W. Howson
Abstract: Methods and apparatus for generating a data structure for storing primitive data for a number of primitives and vertex data for a plurality of vertices, wherein each primitive is defined with reference to one or more of the plurality of vertices. The vertex data comprises data for more than one view, such as a left view and a right view, with vertex parameter values for a first group of vertex parameters being stored separately for each view and vertex parameter values for a second, non-overlapping group of vertex parameters being stored only once and used when rendering either or both views.
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公开(公告)号：US20220269527A1
公开(公告)日：2022-08-25
申请号：US17678335
申请日：2022-02-23
Applicant: Imagination Technologies Limited
Inventor： Panagiotis Velentzas , John W. Howson , Richard Broadhurst
IPC: G06F9/48
Abstract: A method of repacking tasks in a graphics pipeline includes, in response to a task reaching a checkpoint in a program, determining if the task is eligible for repacking. If the task is eligible for repacking, the task is de-scheduled and it is determined whether repacking conditions are satisfied. In the event that the repacking conditions are satisfied, the method looks for a pair of compatible and non-conflicting tasks at the checkpoint. If such a pair of tasks are found, one or more instances are transferred between the pair of tasks.
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公开(公告)号：US11348302B2
公开(公告)日：2022-05-31
申请号：US17111317
申请日：2020-12-03
Applicant: Imagination Technologies Limited
Inventor： John W. Howson , Richard Broadhurst , Steven Fishwick
Abstract: A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.
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公开(公告)号：US20220164919A1
公开(公告)日：2022-05-26
申请号：US17670065
申请日：2022-02-11
Applicant: Imagination Technologies Limited
Inventor： Steven J. Fishwick , John W. Howson
Abstract: A method and system for generating and shading a computer graphics image in a tile based computer graphics system is provided. Geometry data is supplied and a plurality of primitives are derived from the geometry data. One or more modified primitives are then derived from at least one of the plurality of primitives. For each of a plurality of tiles, an object list is derived including data identifying the primitive from which each modified primitive located at least partially within that tile is derived. Alternatively, the object list may include data identifying each modified primitive located at least partially within that tile. Each tile is then shaded for display using its respective object list.
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