公开(公告)号：US20160040282A1

公开(公告)日：2016-02-11

申请号：US14885610

申请日：2015-10-16

Applicant: RAYTHEON COMPANY

Inventor： Roland Gooch ,  Adam M. Kennedy ,  Stephen H. Black ,  Thomas Allan Kocian ,  Buu Diep

IPC: C23C14/28 ,  C23C14/06

CPC classification number: C23C14/28 ,  B32B3/10 ,  B32B15/04 ,  B32B2255/205 ,  B32B2457/00 ,  C23C14/06 ,  G01J5/045 ,  H01L23/26 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

Abstract: A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites.

公开(公告)号：US20160039665A1

公开(公告)日：2016-02-11

申请号：US14456476

申请日：2014-08-11

Applicant: Raytheon Company

Inventor： Adam M. Kennedy ,  Buu Q. Diep ,  Stephen H. Black ,  Tse E. Wong ,  Thomas Allan Kocian ,  Gregory D. Tracy

IPC: B81B7/00

CPC classification number: B81C1/00333 ,  B81B7/0048 ,  B81B7/0051 ,  B81B2201/0207 ,  B81C1/00825 ,  B81C2203/035

Abstract: A sealed package having a device disposed on a wafer structure and slid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

Abstract translation: 一种密封包装，其具有设置在晶片结构上的装置并且被结合到装置晶片上。 器件晶片包括：衬底; 设置在所述装置周围的基板的表面部分上的金属环和设置在所述金属环上的接合材料。 金属环横向延伸超过接合材料的内边缘和外边缘中的至少一个。 金属环的第一层包括具有比衬底的表面部分更高的延展性的应力消除缓冲层，并且具有大于接合材料的宽度的宽度。 金属环横向延伸超出接合材料的内边缘和外边缘中的至少一个。 应力消除缓冲层的热膨胀系数大于衬底表面部分的膨胀系数，小于接合材料的膨胀系数。

公开(公告)号：US09196556B2

公开(公告)日：2015-11-24

申请号：US14193437

申请日：2014-02-28

Applicant: Raytheon Company

Inventor： Roland Gooch ,  Adam M. Kennedy ,  Stephen H. Black ,  Thomas Allan Kocian ,  Buu Diep

IPC: H01L23/26 ,  B32B3/10 ,  B32B15/04

CPC classification number: C23C14/28 ,  B32B3/10 ,  B32B15/04 ,  B32B2255/205 ,  B32B2457/00 ,  C23C14/06 ,  G01J5/045 ,  H01L23/26 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

Abstract: A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites.

Abstract translation: 一种吸气剂结构和方法，其中在结构的表面上形成多个成核位置的条件下，将种子材料层沉积在结构的表面的预定区域上。 成核位置具有小于一分子厚的预定区域的表面积的平均高度。 随后，吸气剂材料沉积在表面上以形成从成核位置向外突出的多个吸气材料构件。

公开(公告)号：US09187312B2

公开(公告)日：2015-11-17

申请号：US14202756

申请日：2014-03-10

Applicant: Raytheon Company

Inventor： Roland Gooch ,  Buu Diep ,  Thomas Allan Kocian ,  Stephen H. Black ,  Adam M. Kennedy

IPC: H01L21/30 ,  B81B7/00 ,  B81C1/00 ,  H01L23/053 ,  H01L23/00

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

公开(公告)号：US20150279755A1

公开(公告)日：2015-10-01

申请号：US14736042

申请日：2015-06-10

Applicant: RAYTHEON COMPANY

Inventor： Roland W. Gooch ,  Buu Q. Diep ,  Adam M. Kennedy ,  Stephen H. Black ,  Thomas A. Kocian

IPC: H01L23/10 ,  H01L23/26 ,  H01L21/52

CPC classification number: H01L23/10 ,  B81B7/0038 ,  B81B2201/0207 ,  B81C1/00269 ,  B81C2203/035 ,  H01L21/52 ,  H01L21/76841 ,  H01L23/26 ,  H01L23/49866 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14683 ,  H01L27/1469 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.

公开(公告)号：US09093444B2

公开(公告)日：2015-07-28

申请号：US13939400

申请日：2013-07-11

Applicant: Raytheon Company

Inventor： Roland W. Gooch ,  Buu Q. Diep ,  Adam M. Kennedy ,  Stephen H. Black ,  Thomas Allan Kocian

IPC: H01L23/48 ,  H01L23/544 ,  H01L23/02 ,  H01L23/06 ,  H01L23/498 ,  H01L21/768 ,  B81B7/00 ,  B81C1/00 ,  H01L23/26 ,  H01L27/146

CPC classification number: H01L23/10 ,  B81B7/0038 ,  B81B2201/0207 ,  B81C1/00269 ,  B81C2203/035 ,  H01L21/52 ,  H01L21/76841 ,  H01L23/26 ,  H01L23/49866 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14683 ,  H01L27/1469 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.

Abstract translation: 电子装置及其制造方法。 一种或多种方法可以包括提供具有空腔和围绕空腔的表面的盖晶片和具有检测器装置和参考装置的装置晶片。 在某些实例中，可以将钛材料的阻焊层沉积到盖晶片的表面上。 可以进一步激活钛材料的阻焊层作为吸气剂。 在各种示例中，盖晶片和器件晶片可以使用焊料接合在一起，并且钛材料的阻焊层可以防止焊料接触盖晶片的表面。

公开(公告)号：US20140124899A1

公开(公告)日：2014-05-08

申请号：US13667458

申请日：2012-11-02

Applicant: RAYTHEON COMPANY

Inventor： Roland Gooch ,  Buu Diep ,  Thomas Allan Kocian ,  Stephen H. Black ,  Adam M. Kennedy

IPC: H01L23/48 ,  H01L23/544 ,  H01L21/56

CPC classification number: B81B7/0041 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/019 ,  H01L23/053 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27444 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/83001 ,  H01L2224/83007 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.