IMAGE LAG MITIGATION FOR BUFFERED DIRECT INJECTION READOUT WITH CURRENT MIRROR
    41.
    发明申请
    IMAGE LAG MITIGATION FOR BUFFERED DIRECT INJECTION READOUT WITH CURRENT MIRROR 有权
    缓冲直射注射的图像延迟缓和电流镜

    公开(公告)号:US20160295146A1

    公开(公告)日:2016-10-06

    申请号:US14673455

    申请日:2015-03-30

    CPC classification number: H04N5/3745 H04N5/33 H04N5/355 H04N5/378

    Abstract: A circuit having a buffered direct injection (BDI) module is provided for image lag mitigation. The BDI module includes an optical detector coupled to a buffer. The buffer has a pixel amplifier which includes no more than two transistors. The BDI module includes a first current mirror coupled to the BDI module. The first current mirror generates a modulating current based on the output of the optical detector. The BDI module further includes a second current mirror coupled to the first current mirror. The second current mirror is configured to generate either an amplified or attenuated photocurrent operable to optimize an imaging time and scene brightness of the optical detector. The BDI module further includes a reset circuit, coupled to the second current mirror, and being configured to reset an integration capacitor which integrates an image signal based on the output of the optical detector.

    Abstract translation: 具有缓冲直接注入(BDI)模块的电路被提供用于图像滞后缓解。 BDI模块包括耦合到缓冲器的光学检测器。 缓冲器具有包括不超过两个晶体管的像素放大器。 BDI模块包括耦合到BDI模块的第一电流镜。 第一电流镜根据光检测器的输出产生调制电流。 BDI模块还包​​括耦合到第一电流镜的第二电流镜。 第二电流镜被配置为产生放大或衰减的光电流,其可操作以优化光学检测器的成像时间和场景亮度。 BDI模块还包​​括耦合到第二电流镜的复位电路,并且被配置为复位基于光学检测器的输出对图像信号进行积分的积分电容器。

    INTEGRATING PIXELS AND METHODS OF OPERATION
    42.
    发明申请
    INTEGRATING PIXELS AND METHODS OF OPERATION 有权
    整合像素和操作方法

    公开(公告)号:US20150281612A1

    公开(公告)日:2015-10-01

    申请号:US14242597

    申请日:2014-04-01

    Abstract: A pixel cell includes a first integration capacitor, a second integration capacitor, a photo detector and a transistor. The first integration capacitor includes a first lead operatively coupled to the photo detector. The second integration capacitor includes a first lead. The transistor is operatively coupled between the leads of the first and second integration capacitors for enabling current flow between the photo detector and the second integration capacitor only once a threshold voltage is met on the first integration capacitor.

    Abstract translation: 像素单元包括第一积分电容器,第二积分电容器,光电检测器和晶体管。 第一积分电容器包括可操作地耦合到光电检测器的第一引线。 第二积分电容器包括第一引线。 晶体管可操作地耦合在第一和第二积分电容器的引线之间,用于仅在第一积分电容器上满足阈值电压时,才使电流在光电检测器和第二积分电容器之间流动。

    PIXEL ARRAY WITH INTERNAL COARSE DIGITIZATION

    公开(公告)号:US20190253656A1

    公开(公告)日:2019-08-15

    申请号:US15895632

    申请日:2018-02-13

    Abstract: A pixel of a pixel array is provided. The pixel includes a low frequency path configured to receive an input signal from a corresponding photodetector. The low frequency path includes a passive imaging circuit provided along the low frequency path, the passive imaging circuit configured to output an analog imaging signal and a flash analog to digital converter (ADC) that receives the analog imaging signal and processes the analog imaging signal to output a coarse digitized signal.

    IMAGING SYSTEMS AND METHODS
    44.
    发明申请

    公开(公告)号:US20190242750A1

    公开(公告)日:2019-08-08

    申请号:US15890263

    申请日:2018-02-06

    Abstract: An imaging method includes assigning pixels within the extent of a focal plane array active area to a first readout range and a second readout range. Image data is read out from the pixels assigned to the first readout range and the second readout range. Pixels located within the extend of the focal plane array active area and not assigned to the first readout range or the second readout range are left unread. Imaging systems and hyperspectral imaging arrangements are also described.

    Event-triggered imaging pixels
    47.
    发明授权

    公开(公告)号:US10154207B2

    公开(公告)日:2018-12-11

    申请号:US15426521

    申请日:2017-02-07

    Abstract: An imaging pixel includes a photodetector for generating a charge signal, an input buffer, a control device, and a switch. The input buffer is connected to the photodetector for amplifying the charge signal. The control device is connected to the photodetector and the input buffer to separate high-frequency charge signals from low frequency charge signals. The switch is operably connected to the input buffer for sampling of high-frequency charge signals in a charge storage device triggered by amplitude of high-frequency charge signals provided by the input buffer.

    In-pixel digital gain and offset corrections

    公开(公告)号:US10044958B1

    公开(公告)日:2018-08-07

    申请号:US15427765

    申请日:2017-02-08

    Abstract: A method includes correcting for at least one of gain and offset during frame integration for photodetector events. Gain and offset correction is performed separately in each pixel of a digital read-out integrated circuit (DROIC) for a plurality of corresponding pixels in a photodetector array. First and second binary counters respectively use a gain register and an offset register to implement gain and offset correction.

    Asynchronous multimode focal plane array

    公开(公告)号:US09948880B2

    公开(公告)日:2018-04-17

    申请号:US15226822

    申请日:2016-08-02

    CPC classification number: H04N5/378 H04N5/2353 H04N5/33 H04N5/332 H04N7/0127

    Abstract: A multimode pixel of a pixel array is provided. The multimode pixel includes a photodetector, an image sensing circuit, a pulse detection circuit, and an image readout path coupled between the image sensing circuit and at least one readout conductor of the pixel array to transmit image signals from the image sensing circuit to the at least one readout conductor. The multimode pixel further includes a pulse readout path different from the image readout path, wherein the pulse readout path is coupled between the pulse detection circuit and the at least one readout conductor to transmit pulse data from the pulse detection circuit to the at least one readout conductor, and wherein the image readout path is controlled independently from the pulse readout path.

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