公开(公告)号：US10068963B2

公开(公告)日：2018-09-04

申请号：US14936370

申请日：2015-11-09

Applicant: United Microelectronics Corp.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee ,  Yu-Ru Yang ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/225 ,  H01L21/768

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

公开(公告)号：US09780230B2

公开(公告)日：2017-10-03

申请号：US15368647

申请日：2016-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/45

CPC classification number: H01L29/7869 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer.

公开(公告)号：US09590041B1

公开(公告)日：2017-03-07

申请号：US14960430

申请日：2015-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ru Yang ,  Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/778 ,  H01L27/092

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/02538 ,  H01L27/092 ,  H01L29/105 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/785

Abstract: A semiconductor structure includes a semiconductor substrate, a dielectric structure formed on the semiconductor substrate and including at least a recess formed therein, a fin formed in the recess, and a dislocation region formed in the fin. The semiconductor substrate includes a first semiconductor material. The fin includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. A topmost portion of the dislocation region is higher than an opening of the recess.

Abstract translation: 半导体结构包括半导体衬底，形成在半导体衬底上并且至少包括形成在其中的凹部的电介质结构，形成在凹部中的鳍和形成在鳍中的位错区。 半导体衬底包括第一半导体材料。 翅片包括第一半导体材料和第二半导体材料。 第二半导体材料的晶格常数与第一半导体材料的晶格常数不同。 位错区域的最高部分高于凹部的开口。

公开(公告)号：US20170040415A1

公开(公告)日：2017-02-09

申请号：US14840038

申请日：2015-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chun-Yuan Wu

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/283 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76232 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有第一区域和第二区域的衬底; 在所述第一区域和所述第二区域上的所述鳍状结构周围形成多个鳍状结构和第一浅沟槽隔离（STI）; 在所述第二区域上形成图案化的硬掩模; 从所述第一区域去除所述鳍状结构和所述第一STI; 在所述第一区域上形成第二STI; 去除图案化的硬掩模; 以及在第二STI上形成栅极结构。

公开(公告)号：US09401429B2

公开(公告)日：2016-07-26

申请号：US13917623

申请日：2013-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

Abstract: A semiconductor structure includes a fin-shaped structure and a gate. The fin-shaped structure is located in a substrate, wherein the fin-shaped structure has a through hole located right below a suspended part. The gate surrounds the suspended part. Moreover, the present invention also provides a semiconductor process including the following steps for forming said semiconductor structure. A substrate is provided. A fin-shaped structure is formed in the substrate, wherein the fin-shaped structure has a bottom part and a top part. A part of the bottom part is removed to form a suspended part in the corresponding top part, thereby forming the suspended part over a through hole. A gate is formed to surround the suspended part.

Abstract translation: 半导体结构包括鳍状结构和栅极。 鳍状结构位于基板中，其中鳍状结构具有位于悬挂部分正下方的通孔。 门围绕悬挂部分。 此外，本发明还提供一种半导体工艺，包括用于形成所述半导体结构的以下步骤。 提供基板。 在基板上形成翅片状结构，其中，翅片状结构具有底部和顶部。 底部的一部分被去除以在相应的顶部部分中形成悬挂部分，从而在悬空部分上形成通孔。 形成围绕悬挂部分的门。

公开(公告)号：US20160211144A1

公开(公告)日：2016-07-21

申请号：US14631807

申请日：2015-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chih-Chien Liu ,  Hsin-Kuo Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3065

CPC classification number: H01L21/30608 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/785

Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.

Abstract translation: 施加光照射的外延工艺包括以下步骤。 提供基板。 执行干蚀刻工艺和湿蚀刻工艺以在衬底中形成凹部，其中在执行湿蚀刻工艺时红外光照亮。 在凹部中形成外延结构。

公开(公告)号：US20160148816A1

公开(公告)日：2016-05-26

申请号：US14549529

申请日：2014-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rung-Yuan Lee ,  Yu-Ting Li ,  Jing-Yin Jhang ,  Chen-Yi Weng ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Wei-Jen Wu ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Wen-Chin Lin ,  Chih-Chien Liu ,  Chih-Hsun Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/28

CPC classification number: H01L21/30625 ,  H01L21/28123 ,  H01L21/32115 ,  H01L21/3212

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成第一材料层; 在所述第一材料层上形成停止层; 在所述停止层上形成第二材料层; 并且进行平面化处理以去除第二材料层，停止层以及用于形成栅极层的第一材料层的一部分。

公开(公告)号：US20160111527A1

公开(公告)日：2016-04-21

申请号：US14979594

申请日：2015-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Hsin-Kuo Hsu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/36 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device with fin-shaped structure is disclosed. The method includes the steps of: forming a fin-shaped structure on a substrate; forming a first dielectric layer on the substrate and the fin-shaped structure; depositing a second dielectric layer on the first dielectric layer; etching back a portion of the second dielectric layer; removing part of the first dielectric layer to expose a top surface and part of the sidewall of the fin-shaped structure; forming an epitaxial layer to cover the exposed top surface and part of the sidewall of the fin-shaped structure; and removing a portion of the second dielectric layer.

Abstract translation: 公开了一种制造具有鳍状结构的半导体器件的方法。 该方法包括以下步骤：在衬底上形成鳍状结构; 在所述基板上形成第一电介质层和所述鳍状结构; 在所述第一电介质层上沉积第二电介质层; 蚀刻第二介电层的一部分; 去除所述第一电介质层的一部分以暴露所述鳍状结构的顶表面和所述侧壁的一部分; 形成外延层以覆盖所述鳍状结构的暴露的顶表面和所述侧壁的一部分; 以及去除所述第二电介质层的一部分。

公开(公告)号：US09263579B2

公开(公告)日：2016-02-16

申请号：US14723447

申请日：2015-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Chun-Yuan Wu ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Yu-Shu Lin ,  Szu-Hao Lai

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/30 ,  H01L29/66 ,  H01L29/165 ,  H01L21/306 ,  H01L21/324 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3003 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636

Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.

公开(公告)号：US20150357190A1

公开(公告)日：2015-12-10

申请号：US14312707

申请日：2014-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Hsin-Kuo Hsu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/02 ,  H01L29/36 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/36 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A semiconductor device with fin-shaped structure is disclosed. The semiconductor device includes: a substrate; a fin-shaped structure on the substrate; and an epitaxial layer on a top surface and part of the sidewall of the fin-shaped structure, in which the epitaxial layer and the fin-shaped structure includes a linear gradient of germanium concentration therebetween.

Abstract translation: 公开了一种具有鳍状结构的半导体器件。 半导体器件包括：衬底; 基板上的鳍状结构; 以及在鳍状结构的顶表面和侧壁的一部分上的外延层，其中外延层和鳍状结构在其间包括锗浓度的线性梯度。