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    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
    41.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20250096000A1

    公开(公告)日：2025-03-20

    申请号：US18487141

    申请日：2023-10-16

    Applicant: United Microelectronics Corp.

    Inventor： Kun-Ju Li ,  Hsin-Jung Liu ,  Jhih Yuan Chen ,  I-Ming Lai ,  Ang Chan ,  Wei Xin Gao ,  Hsiang Chi Chien ,  Hao-Che Hsu ,  Chau Chung Hou ,  Zong Sian Wu

    IPC: H01L21/304 ,  H01L21/306 ,  H01L21/762

    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.

    ALIGNMENT MARK STRUCTURE AND METHOD OF FABRICATING THE SAME
    43.
    发明申请
    ALIGNMENT MARK STRUCTURE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210249357A1

    公开(公告)日：2021-08-12

    申请号：US16786919

    申请日：2020-02-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Jhih-Yuan Chen ,  Hsin-Jung Liu ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Fu-Chun Hsiao ,  Ji-Min Lin ,  Chun-Han Chen

    IPC: H01L23/544 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

    Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer are independently comprises silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

    Manufacturing method of memory device
    45.
    发明授权
    Manufacturing method of memory device 有权

    公开(公告)号：US10804461B1

    公开(公告)日：2020-10-13

    申请号：US16517693

    申请日：2019-07-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Jung Liu ,  Kun-Ju Li ,  Ang Chan ,  Chau-Chung Hou ,  Yu-Lung Shih

    IPC: H01L21/00 ,  H01L43/12 ,  H01L43/02

    Abstract: A method for manufacturing a memory device is provided, the method includes the following steps: firstly, providing a dielectric layer, then simultaneously forming a contact window and an alignment mark trench in the dielectric layer, wherein the contact window exposes a lower metal line, then forming a conductive layer on the surface of the dielectric layer, in the contact window and in the alignment mark trench, performing a planarization step on the conductive layer, and leaving a residue in the alignment mark trench. Subsequently, a nitrogen plasma step (N2 plasma) is performed on the dielectric layer, a cleaning step is performed to remove the residue in the alignment mark trench, and a patterned magnetic tunneling junction, MTJ) film is laminated on the contact window.

    Wafer polishing pad and using method thereof
    46.
    发明授权
    Wafer polishing pad and using method thereof 有权

    公开(公告)号：US10722998B2

    公开(公告)日：2020-07-28

    申请号：US15719515

    申请日：2017-09-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chun-Liang Liu

    IPC: B24B37/24 ,  B24B37/22 ,  B24B37/26

    Abstract: The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.

    Method of manufacturing embedded magnetoresistive random access memory
    48.
    发明授权
    Method of manufacturing embedded magnetoresistive random access memory 有权

    公开(公告)号：US10535817B1

    公开(公告)日：2020-01-14

    申请号：US16144888

    申请日：2018-09-27

    Applicant: United Microelectronics Corp.

    Inventor： Ching-Wen Hung ,  Kun-Ju Li

    IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/08

    Abstract: A method of manufacturing an embedded magnetoresistive random access memory including the following steps is provided. A memory cell stack structure is formed on a substrate structure. The memory cell stack structure includes a first electrode, a second electrode, and a magnetic tunnel junction structure. A first dielectric layer covering the memory cell stack structure is formed. A metal nitride layer is formed on the first dielectric layer. A second dielectric layer is formed on the metal nitride layer. A first CMP process is performed on the second dielectric layer to expose the metal nitride layer by using the metal nitride layer as a stop layer. An etch back process is performed to completely remove the metal nitride layer and expose the first dielectric layer. A second CMP process is performed to expose the second electrode. The manufacturing method can have a better planarization effect.

    WAFER POLISHING PAD AND USING METHOD THEREOF
    50.
    发明申请
    WAFER POLISHING PAD AND USING METHOD THEREOF 审中-公开

    公开(公告)号：US20190070706A1

    公开(公告)日：2019-03-07

    申请号：US15719515

    申请日：2017-09-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chun-Liang Liu

    IPC: B24B37/22 ,  B24B37/26

    CPC classification number: B24B37/22 ,  B24B37/24 ,  B24B37/26 ,  B24D2205/00

    Abstract: The present invention provides a wafer polishing pad, the wafer polishing pad includes a polishing material layer, a plurality of recesses are formed on the top surface of the polishing material layer, and a warning element disposed within the polishing material layer, the warning element and the polishing material layer have different colors. The feature of the invention is that forming a warning element in the polishing material layer, when the visible state of the warning element is changed, for example, when the warning element appears, disappears or changes the shapes, it means that the wafer polishing pad needs to be replaced. In this way, the user can confirm the destroying situation of the wafer polishing pad easily, and also improving the manufacturing process efficiency.

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